The CSC Track-Finding Processor
D.Acosta
University of Florida
CSC Muon Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver
Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
In counting house
CSC Muon Sorter
RPC
On chamber
4µ
In chamber crate
DT
4µ
Global µ Trigger
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
4µ
4µ
Global L1
2
Muon Track-Finding
• Link trigger primitives into tracks
• Assign PT, ϕ, and η
• Send highest PT candidates to Global L1 trigger
θ
ϕ
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
3
CSC Track-Finder Requirements
• Trigger Rate:
Single muon rate < few kHz at L = 1034cm-2 s-1
• Resolution:
σPt / Pt ≤ 30%
•
•
•
•
•
•
•
•
Threshold:
Selection:
Redundancy:
Latency:
Pipelined
High Efficiency
Programmable
Test features
D. Acosta, Univ. of Florida
(Requires η information)
Pt > 3 GeV
≤ 3 muons per 60° sector
Require 2 stations out of 3 or 4
≤ 16 b.x. for Sector Processor
TriDAS Review, Nov. 1998
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Trigger Regions in η
0.9
2.4
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
5
Trigger Regions in ϕ
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
6
Track Segments per Sector
Region Station
CSC
OVL
1
2
3
4
1
2
3
4
Chamber Segments No. of ϕ No. of
Extrapper sector sectors segments olations
ME1
ME2
ME3
ME4
MB1
MB2
ME1
ME2
3
3
3
3
2
2
3
3
2
1
1
1
2
2
2
1
6
3
3
3
4
4
6
3
81
106
• Neighbors in ϕ are not considered:
• CSC chambers project in ϕ
• ∆ϕ12 < 3° for PT > 10 GeV
• Neighbors in η do not exist
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
7
Differences between CSC and DT Track-Finders
• No neighbor input for CSC T-F implies
–
–
–
–
Fewer extrapolations
Less data input
Fewer signals to fan out
Less opportunity for two tracks to arise from one muon
• Inclusion of η in CSC T-F allows
– Precise PT assignment in endcap
– Track-Finding in 3 dimensions
– Rate reduction
• Therefore, CSC T-F is fundamentally different than DT T-F
• Coverage of overlap region in CSC T-F complements approach taken
by DT T-F
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
8
Required Precision of Data
• Azimuthal angle ϕ:
– 12 bits / 60° ⇒ 1 bit / 0.26 mrad (0.1 strip)
• Bend angle Ψ:
– 6 bits / ±45° ⇒ 1 bit / 60 mrad
• Polar angle η:
– B-field variation < ±3% for 0.05 unit bins
– 5 bits / 1.5 units ⇒ 1 bit / 0.05
ϕ2
Ψ
ϕ1
∆ϕ
• Quality:
– 3 bits
• Full precision needed for PT assignment only, not extrapolation
– e.g.
ϕ : 7 bits
D. Acosta, Univ. of Florida
∆ϕ : 6 bits
TriDAS Review, Nov. 1998
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Inputs to CSC Sector Processor
1 CSC stub = 12 ϕ bits + 6 Ψ bits + 5 η bits + 3 Q bits = 26 bits
1 Port Card sends 3 stubs
1 Sector Receiver accepts 2 Port Cards = 6 stubs
1 Sector Processor accepts 6 + 3 + 3 + 3 = 15 stubs (divided between 2.5
Sector Receivers)
• 15 stubs × 26 bits = 390 bits
•
•
•
•
CSC crate: 9U VME with custom point-to-point backplane for last 3U
S
R
C
S
C
S
R
C
S
C
ME 1
ME
2,3
SP
156
S
R
C
S
C
S
R
C
S
C
S
R
C
S
C
ME 4
ME 1
ME
2,3
SP
D. Acosta, Univ. of Florida
S
R
C
S
C
S
R
C
S
C
ME 4
ME 1
ME
2,3
156
78
156
S
R
C
S
C
S
R
C
S
C
SP
ME 4
156
78
78
156
TriDAS Review, Nov. 1998
156
10
Inputs to OVL Sector Processor
•
•
•
•
•
1 CSC stub = 26 bits
1 DT stub = 11 ϕ bits + 8 Ψ bits + 3 Q bits = 22 bits
1 Sector Processor accepts 4+4 DT stubs and
6+3 CSC stubs
= 410 bits
(8 DT stubs × 22 bits) + (9 CSC stubs × 26 bits)
DT stubs sent from DT trigger fan-out unit
OVL crate: 9U VME with custom point-to-point backplane for last 3U
S
R
C
S
C
S
R
C
S
C
ME 1
ME 2
SP
78
156
D. Acosta, Univ. of Florida
D
T
MB
1,2
176
S
R
C
S
C
S
R
C
S
C
ME 1
ME 2
SP
78
D
T
MB
1,2
176
156
TriDAS Review, Nov. 1998
S
R
C
S
C
S
R
C
S
C
ME 1
ME 2
SP
78
D
T
MB
1,2
176
156
11
CSC Track-Finder Crate Organization
Endcap 1
360°
Endcap 2
CSC
OVL
OVL
CSC
Rack 1
Rack 2
Rack 3
Rack 4
180°
ϕ
0°
CSC Counting House electronics:
Racks: 4
Crates: 8 (including power supply, controller, CCC)
Sector Processors: 24
Sector Receivers: 48
Muon Sorter: 1
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
12
Sector Receiver Functionality
• Receives 6 stubs via optical links from 2 Port Cards
• Synchronizes the data
• Reformats the data
– LCT bit pattern → η, ϕ, Ψ
• Communicates to Sector Processor via custom point-to-point backplane
• Fans out signals to CSC overlap processors and sends ME1/3 signals
to DT Sector Processor
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
13
Sector Processor Functionality
• Sector Processor must identify muons from ~400 bits every 25ns (2 GB/s)
1. Perform all possible station-to-station extrapolations in parallel
Simultaneously search for roads in ϕ and η
2. Assemble 3- and 4-station tracks from 2-station extrapolations
3. Cancel redundant short tracks if track is 3 or 4 stations in length
4. Select the three best candidates
5. Calculate PT, ϕ, η and send to CSC muon sorter:
Quantity
η
ϕ
Muon sign
PT
Quality
Precision
6 bits
8 bits
1 bit
5 bits (nonlinear)
2 bits
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
14
Sector Processor Block Diagram
2
1*
3
1**
3
2
3
2
4
3x21
3x21
3x21
3x21
3x21
3x21
3x21
3x21
3x21
3-4
VME BUS
Final Selection Unit
Pt
LID
FIFO
3x21
FIG.1. TRACK FINDING PROCESSOR. BLOCK DIAGRAM.
TriDAS Review, Nov. 1998
LOOK-UP
Output Data
3x22 = 66
OUTPUT
CONNECTOR
MUX
CLOCKED
NOVEMBER, 2nd.
D. Acosta, Univ. of Florida
9x2
2-4
QTA 3x22
LID - Look-Up Input Data
FIFO
(3-4)
15x1
( 1-2-3-4 )
STA
EU - Extrapolation Unit
QSU - Quality Selection Unit
TAU - Track Assembling Unit
FSU - Final Selection Unit
DTA - Double Track Assemblage
TTA - Tripple Track Assemblage
QTA - Quadruple Track Assemblage
STA - Selected Track Address
Quality Selection
Units
QSU 5
DOWNLOADING/
READOUT
INTERFACE
TTA 3x16
TAU 2
1111111111111
0000000000000
3x7
2-4
3x7
2-3
3x7
1-3
DTA 3x10
3x11
2-3-4
3x11
1-3-4
3x11
1-2-4
3x11
- Control Line
- Downloading/
Readout Line
QSU 4
(2-4)
FSU
(1-2-3, 1-2-4, 1-3-4, 2-3-4 )
1-2-3
9x2
QSU 3
(2-3)
Extrapolation Units
EU 3 - 4
Track Assembler
TAU 1
- Data Line
EU 2 - 4
4
3x21
3x7
3-4
3x7
2-4
3x7
2-3
3x7
3x7
1-3
1-2
3x7
1-2
15x26=390
Input Data
INPUT DATA &
CONTROL
INTERFACE
9U
CUSTOM
BACKPLANE
2-3
QSU 2
(1-3)
(1-2)
Control
EU 2 - 3
9x2
9x2
1* - 3
9x2
QSU 1
Data
EU 1** - 3
1** - 3
EU 1* - 3
1** - 2
Input
EU 1** - 2
9x2
1*- 2
EU 1* - 2
3
3x21
9x2
1**
3x21
3-4
2
3x21
3x7
1*
3x21
Assignment Unit
and Output
01
15
Extrapolation Unit Detail
η1
5
η2
5
η1−η2
6
LUT
SM
& Match η
64x1
η1
5
η road finder
η1−η2
LUT
LUT
32x6
32x1
η2
5
LUT
LUT
32x6
32x2
Input Data
42 Bits
η1
η2
5
5
φ1
7
φ2
ψ1
SL
MUX
2x1
5
8
7
SM
φ1−φ2
6
LUT
LUT
32x6
6
6
6
6
LUT
6
CMP
η∗, ∆φ
6
CMP
η∗∗, ∆φ
6
CMP
η∗∗∗, ∆φ
3
LUT
6
6
6
64x6
Q1 3
Q2 3
6
PRE
LUT
16x2
2
3-2
Match φ
2
Output Data
2
&
q1,q2
Result quality
Coarse PT assign
&
8x1
6
ψ2
z
SM
7
∆φ−ψ1
SM
7
∆φ−ψ2
LUT
Match ψ1
128x1
LUT
Match ψ2
ϕ road finder
128x1
ϕ
2
64x2
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
16
Implementation Technology
• Sector Processor logic to be implemented in FPGAs and RAM
• Attempt to run some logic at 80 MHz
• Study of Xilinx FPGA implementation of Extrapolation Unit only:
–
–
–
–
–
Small number of chips needed for extrapolation (3)
Number of I/O pins needed per chip under control (~250)
Logic size under control (~60K gates)
No external RAM needed
Routing resources inside chip limits minimum chip size
• Complication of η dependence for PT assignment under control ⇒
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
17
Assignment Unit
ϕ1
ϕ2
LUT
4K x 7
φ2 6 MSB
φ1 6 MSB
∆φ2
4 LSB
LUT
4K x 7
φ2 6 LSB
Station I.d.
Pt 5 Bits
∆φ1
6 Bits
φ1 6 LSB
η
LUT
256K x 5
PT
CO1
η 4 Bits
ID 3 Bits
LUT
1M x 8
η 4 Bits
φ Out 8 Bits
ID 3 Bits
φ2 6 MSB
ϕ
φ1 6 MSB
Clock RAMs at 80 MHz
⇒ 1 b.x. delay only
η 4 Bits
Q 3 Bits
D. Acosta, Univ. of Florida
LUT
16 x 6
LUT
8x2
TriDAS Review, Nov. 1998
η Out 6 Bits
Q Out 2 Bits
η
quality
18
CSC Muon Sorter
• The three highest rank muons from each Sector Processor are sent to
the CSC muon sorter, which then selects the four highest rank overall
• Total muon count:
– 3 muons × 6 sectors × 2 endcaps = 36 muons
× 2 = 72 muons
–
for CSC only
for CSC and OVL regions
• For comparison, the DT muon sorter accepts 24 muons
• Sort is based on 7 bits (5 bits for PT and 2 bits for quality)
• One sorter card is necessary for entire CSC+OVL
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
19
Milestones / Schedule
å
å
•
•
•
•
•
•
•
•
•
•
•
•
D387 – 1999 Mar, Sector Receiver Initial System Design
D331 – 1999 Mar, Sector Processor Initial System Design
D390 – 1999 Sep, Sector Receiver Prototype Design
D332 – 1999 Sep, Sector Processor Prototype Design
D391 – 2000 Jan, Sector Receiver Prototype
D334 – 2000 Jan, Sector Processor Prototype
D335 – 2000 Apr, Sector Receiver / Processor Crate Test
Dnnn – 2001 Sep, Sector Receiver Final Design
Dnnn – 2002 Apr, Sector Processor Final Design
Dnnn – 2003 May, Sector Receiver Produced
Dnnn – 2003 Aug, Sector Processor Produced
Dnnn – 2003 Oct, Sector Receiver Installed
Dnnn – 2004 Jan, Sector Processor Installed
Dnnn – 2004 Sep, Trigger System Tested
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
20
Documentation
• Can be found at:
– http://www.phys.ufl.edu/~acosta/cms/trigger.html
• Includes more detailed design descriptions and some simulation results
D. Acosta, Univ. of Florida
TriDAS Review, Nov. 1998
22