Status of the CSC Track-Finder
Darin Acosta
University of Florida
CSC Muon Trigger Scheme
TriDAS part: Second
generation prototypes
EMU part: mostly in production
Muon Portcard (1)
Trigger Motherboard (9)
Clock Control Board
Trigger
Timing &
Control
D T D TD T D T D T CMT DT D T D T D
M M M MM M M M M M C P M MM M M MM M
C BB B BB BB B B B B CB BB B B BB B
O
N
T
R
O
L
L
E
R
Optical
link
Muon
Sorter (1)
Sector
Processor (12)
CFEB CFEB CFEB CFEB CFEB
CSC Track-Finder
Crate (1)
In underground
counting room
3-D Track-Finding
and Measurement
CMS Week, 25 Feb 2003
DAQ Motherboard (9)
LVDB
ALCT
Peripheral Crate
on iron disk (1 of 48)
Cathode Front-end Board
Anode LCT Board
On detector
Trigger
Primitives
2
CSC
Anode Front-end Board
D.Acosta, University of Florida
1st Prototype Track-Finder Tests (2000)
Sector Processor
(Florida)
Sector Receiver Clock Control
(UCLA)
Board (Rice)
Bit3
VME
Interface
Very
successful,
but overall
CSC latency
was too high -New 2002
design
improves
latency
Custom
ChannelLink
Backplane
(Florida)
Results
included in
Trigger L1
TDR
CMS Week, 25 Feb 2003
Muon Port Card
(Rice)
3
D.Acosta, University of Florida
CSC Track-Finder Crate
Muon Sorter
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
MS
CCB
Clock and Control
Board
SBS 620 Controller
Second generation prototypes
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
Sector Processor
From MPC
(chamber 4)
From MPC
(chamber 3)
From MPC
(chamber 2)
From MPC
(chamber 1B)
4 merged
boards
From MPC
(chamber 1A)
To DAQ
Single Track-Finder Crate Design with 1.6 Gbit/s optical links
CMS Week, 25 Feb 2003
4
D.Acosta, University of Florida
Combined SR/SP 2002 Prototype
Problems encountered
attempting layout using
in-house tools
 Sent to industry for
completion of layout
using Cadence Allegro
 Final board takes 16
layers
 Cost of manufacture,
assembly, and parts is
about $20K / board

CMS Week, 25 Feb 2003
5
D.Acosta, University of Florida
SP2002 Main Board (SR Logic)
DC-DC Converter
EEPROM
Phi Global
LUT
VME/
CCB
FPGA
Eta Global
LUT
Phi Local
LUT
TLK2501
Transceiver
Front
FPGA
Optical
Transceivers
•15 x 1.6
Gbit/s Links
3 SRs
CMS Week, 25 Feb 2003
6
D.Acosta, University of Florida
SP Trigger Logic
From SP2000
to SP2002 mezzanine card
Xilinx Virtex-2 XC2V4000
~800 user I/O
(Mezzanine card also used for CSC sorter)
CMS Week, 25 Feb 2003
7
D.Acosta, University of Florida
Tests underway…
CMS Week, 25 Feb 2003
8
D.Acosta, University of Florida
Optical Link Test Results
Using pseudo-random test built into TLK2501 chipset
SP02 optical loopback test over 1 m optical cable
 No errors!
 SP02 optical loopback test over 100 m cable
 BER = 1012
 MPCSP02 optical test over 100 m cable
 BER = 3×1013

Controlled MPCSP02 chain test
Download 255 bx of data for one MPC (3 muons × 32 bits),
preceding each iteration with a L1 Reset
 Send data over three 100 m cables into SP, and readout
 Counting the 0’s transmitted between iterations, 30 link
errors observed in total from 3 links over 16 hours (3×1014
bits)
 BER = 1013

Thus, about 1 error / hour, likely from clock jitter
CMS Week, 25 Feb 2003
9
D.Acosta, University of Florida
Optical Link Tests (Cont’d)
Controlled MPCSP02 chain test without L1 Reset
This is how we would like to operate
 Explicitly check data sent vs. data received
 Tests underway, code still needs improvements (e.g. to issue
L1 Reset if link fails and does not recover)

CMS Week, 25 Feb 2003
10
D.Acosta, University of Florida
Schedule
Proposed schedule as of Feb-2003:
Feb.’03: SP02 prototype completed, initial tests begin √
 Mar.’03: MPCSP optical link tests
√ (April)
 Apr.’03: SP memory and trigger logic tests
 May.’03: CSC system tests with cosmic rays and
beam tests at CERN


June ’03… : Tests with Muon Sorter and DT Track-Finder
CMS Week, 25 Feb 2003
11
D.Acosta, University of Florida
Test Beam Plans
Plan to test CSC Trigger all the way to the Track-Finder
in May/June beam tests
Complete chain test from 2 detectors to peripheral crate
electronics to Track-Finder crate electronics!

Structured beam period: 23 May  1 June
Two DAQ systems will run concurrently: CSC DAQ and
Track-Finder DAQ
 Track-Finder will just log inputs, not generate a track trigger
 Goal is to validate trigger primitives are found efficiently on
correct bx and successfully received over optical links
 Record as much data as possible under various detector
configurations for future track identification studies

Asynchronous beam period: 13 June  1 July
Possibility to test a unified DAQ using “slice test” software
developed in XDAQ

CMS Week, 25 Feb 2003
12
D.Acosta, University of Florida
Conclusions
Second generation CSC Track-Finder prototype
completed
Optical link tests between Port Card and Sector
Receiver successful

Measurable (but small ~10-13) bit error rate seen
Plan to take T-F to beam test later this month
Tests of SR memories and SP trigger logic to follow
Interface tests with CSC Sorter and DT T-F also planned
CMS Week, 25 Feb 2003
13
D.Acosta, University of Florida