Status of the CSC Track
-Finder
Track-Finder
Darin Acosta
University of Florida
May 2000
D. Acosta, University of Florida
TriDAS Review May 2000
1
Outline
Overview of the CSC trigger system
Sector Receiver
Sector Processor
Muon Sorter
CSC/DT Interface
D. Acosta, University of Florida
TriDAS Review May 2000
2
CSC Muon Trigger Scheme
Strip LCT +
Motherboard
card
Strip FE cards
CSC Track-Finder
Sector
Sector
Receiver
Processor
Port Card
LCT
OPTICAL
FE
SR
PC
SP
LCT
3µ / port card
TMB
FE
2µ / chamber
Wire LCT card
Wire FE cards
3µ / sector
In
counting
house
RIM
CSC Muon Sorter
RPC Interface
Module
On chamber
D. Acosta, University of Florida
RPC
4µ
In peripheral
crate
DT
4µ
4µ
Global µ Trigger
TriDAS Review May 2000
Global L1
4µ
3
The CSC Track
-Finder
Track-Finder
From DT
Track-Finder
(Vienna)
12 Sector
Processors
MB1
DT TF
1 Muon Sorter
SP
ME4
OPTICAL
(Vienna)
ME2-ME3
To Global
Muon
Trigger
ME1
SR
From CSC
Port Cards
PC
3µ / port card
WBS:
3.1.1.1
D. Acosta, University of Florida
SP
24 Sector
Receivers
MS
3µ / sector
12 sectors
4µ
GMT
(+12 for ME4)
(UCLA)
(Florida)
3.1.1.2
3.1.1.3,
3.1.1.4
TriDAS Review May 2000
(Rice)
3.1.1.15
4µ
From DT
8µ
Track-Finder
RPC
4
UCLA
Sector Receiver Functionality
3.1.1.2
1. Receive 6 µ segments via 12 optical links
from 2 Muon Port Cards
• Require 3 Sector Receivers for one 60°
sector
2. Synchronize the data
3. Reformat the data into track segment
variables
via LUTs
• LCT bit pattern → η, ϕ, ϕb, ...
4. Apply corrections for alignment
5. Communicate to Sector Processor via
custom backplane (Channel Link)
6. Fan out ME1/3 µ segments to DT TrackFinder
}
D. Acosta, University of Florida
TriDAS Review May 2000
5
UCLA
Sector Receiver Logic
3.1.1.2
Front
Panel
Optical
Fiber
from
MPC
Optical
Fiber
from
MPC
VME
JTAG
interface
Optical
Receiver
Controller
FPGA
Deserializer
Front
FPGA
Optical
Receiver
Deserializer
L
U
T
S
L
U
T
S
Back
FPGA
To
Backplane
Repeat for each Muon
D. Acosta, University of Florida
TriDAS Review May 2000
To
Barrel
6
D. Acosta, University of Florida
TriDAS Review May 2000
7
UCLA
Sector Receiver LUT Scheme
UCLA
Sector Receiver
• Fell behind schedule after postdoc departure.
3.1.1.2
• Personnel added in December/January:
• Robert Cousins, physicist, 50% time
• Vladislav Sedov, electronics engineer, 90% time
(10% residual work on ALCT board)
• Also using paid consultant for some FPGA work
(UCLA CS Ph.D. candidate)
• Schematics now well underway.
• Long-lead-time parts ordered.
• Layout planned by beginning of May.
• Plan to be ready for summer Track Finder test.
D. Acosta, University of Florida
TriDAS Review May 2000
8
Florida
Sector Processor Functionality
3.1.1.3,
1. Accumulate track segments for possibly
3.1.1.4
more than one B.X.
2. Extrapolate in 3D from one station to another
for all possible track segment combinations
3. Assemble tracks from extrapolation results
4. Select best 3 tracks and cancel ghosts
5. Assign track parameters: pT, ϕ, η, quality
New since last Review:
• Combined DT/CSC overlap region onto same board
as CSC-only region (add MB1–ME2 extrap.)
• Improved PT assignment technique
• Ghost-busting when 2 muons enter
1 CSC chamber (try all combinations)
D. Acosta, University of Florida
TriDAS Review May 2000
1
2
1
2
9
Florida
Sector Processor Logic
Extrapolation
Units
bus
Bunch
Crossing
Analyzer
From
Backplane
BXA
EU1-2
3.1.1.3,
3.1.1.4
Track Assembler
Units
bus
TAU1
Final
Selection
Unit
EU1-3
EU2-3
TAU2
FSU
EU2-4
Assignment
Unit
EU3-4
TAU3
EU
MB1-2
AU
FIFO
D. Acosta, University of Florida
TriDAS Review May 2000
To Front
panel
MUX
10
Florida
Extrapolation Logic
A m b (A 1 )
η ro a dfinder
fin d er
η road
Q η( A 1 B 1) Q η( A 2 B 1) Q η( A 3 B 1)
A m b (B 1 )
LUT
η1
η (A 1 )
η (B 1 )
“AN D”
SUB
η A-η B
“O R”
LUT
∆ η
z
LUT
η2
CM P
∆ φ h ig h
LUT
∆ φ h ig h
LUT
∆ φ m ed
CM P
∆ φ m ed
Q e x tr a p (A 1 B 1 )
LUT
E x tr a p
Q u al
LUT
∆ φ lo w
q u a lity
aquality
ssign m en t
uassignment
n it
CM P
∆ φ lo w
AB S
∆ φ
Q u al(A 1 )
unit
Q u al(B 1 )
LUT
φ b+
LUT
φ b-
φ b (A 1 )
φ (A 1 )
φ (B 1 )
φ b (B 1 )
CM P
∆ φ -φ b+
CM P
∆ φ -φ b-
SUB
φ A -φ B
LUT
∆ φ
LUT
φ b+
LUT
φ b-
“AND”
CM P
∆ φ -φ b+
ϕ
CM P
∆ φ -φ b-
ϕϕroroad
a d finfinder
d er
D. Acosta, University of Florida
TriDAS Review May 2000
11
Florida
Track Selection and
PTT Assignment
φ
LUT
φ
η
“9 to 3” Sorter with
ghost cancellation logic
FIFO
MUX
LUT
η
SUB
φ1-φ2
MUX
9 Track Assembler RAMs
MUX
φ3
η
Rank
(PT &
Quality)
φ1
φ2
φ
~2M x 8
SRAM
LUT
Sign
SUB
φ2-φ3
Mode
(From FSU)
I.D.
Comparison
Unit
Track
Rank
Sorter
D. Acosta, University of Florida
Cancellation
Logic and
Encoder
New: 3-station sagitta measurement using
FPGA preprocessing and RAM
(Improves PT resolution from 30% to 20%)
TriDAS Review May 2000
12
Standard VME
Florida
SP Prototype Layout
VME/JTAG interface (developed separately)
Extrapolation Track
Bunch
Final
Crossing Units
Assembler Selection
Analyzer
Unit
Units
XCV50BG256 XCV400BG560
SRAM
Assignment
Units
• Layout
complete
• 12 layers
XCV150BG352
XCV50BG256
• Tests set
for 6/1/00
Custom ChannelLink backplane
SRAM
D. Acosta, University of Florida
TriDAS Review May 2000
13
Florida
Prototype Crate Layout
SR
SR
SP
SR
CCB
3.1.1.7
One sector is
half of TrackFinder crate
Fully routed
for summer
tests
Six crates for
entire system
Smaller
prototype
tested already
US CMS DOE/NSF Review: April 11-13, 2000
13
Florida
Pre
-Prototype Tests
Pre-Prototype
VME / JTAG interface for
SR and SP:
Software & hardware for
FPGA and SRAM
downloading through
VME works
Channel Link
backplane and
connector tests:
No errors found
up to 58 MHz
clock (400 MHz
on backplane)
D. Acosta, University of Florida
TriDAS Review May 2000
15
Rice
Muon Sorter Functionality
3.1.1.15
1. Receive 36 muons from 12 Sector Processors
• 36 × 18 bits = 648 bits (& control bits)
2. Sort and rank the best 4 muons
• Sort is based on 7 bits (5 bits for pT and 2 bits
for quality)
3. Send the output to the Global Muon Trigger for
association with RPC and DT triggers
• 4 × 22 bits = 88 bits
New since last Review:
• Reduction in muon count from 72 to 36
(inclusion of CSC/DT overlap in Sector Processor)
allows sorting to be accomplished in one FPGA
D. Acosta, University of Florida
TriDAS Review May 2000
16
Rice
Muon Sorter Logic
FF- FLIP-FLOP, LUT - LOOK-UP TABLE RAM
3.1.1.15
VME INTERFACE
FOR LUT READ/WRITE
28
FF 28
28
FF 28
28
FF 28
28
FF 28
28
14
FF 14
FF 28
28
FF 28
28
28
28
CLK
40MHz
FF 28
FF 2
8
SORTER
7+6
4 out of 18
7+6
6
FF
6
ADR1
7
LUT 8
PAT1
7+6 SORTER
153
comparisons 7+6 4 out of 8
in parallel
SORTER
7+6
28
4 out of 18
7+6 comparisons
in parallel
7+6
153
comparisons 7+6
in parallel
6
FF
6
ADR2
7
LUT 8
PAT2
6
FF
6
ADR3
7
LUT 8
PAT3
6
FF
6
ADR4
7
LUT 8
PAT4
ALTERA EP20K200EFC484-1
0
1
2
3
4
“4 out of 36” SINGLE-CHIP SORTER BLOCK DIAGRAM AND TIMING
D. Acosta, University of Florida
TriDAS Review May 2000
17
Rice
Sorter Board Block Diagram
3.1.1.15
CONNECTORS
TO GMT
9U * 400 MM
BOARD
VME
INTERFACE
CCB
INTERFACE
GMT LVDS
DRIVERS
VME J1
CONNECTOR
CONNECTOR
TO CUSTOM
BACKPLANE
252
SORTER
PLD
D. Acosta, University of Florida
CONNECTOR TO
RECEIVER BOARDS
56
TriDAS Review May 2000
18
Rice
Muon Sorter Crate Layout
S
R
R
R
3.1.1.15
R
CONNECTORS
TO GMT
12 CONNECTORS TO
RECEIVER BOARDS
D. Acosta, University of Florida
TriDAS Review May 2000
19
Rice
Sorter Receiver Board
Block Diagram
3.1.1.15
POWER
RECEIVERS
CLOCK
CONNECTOR
TO SP
CONNECTOR
TO SP
CONNECTOR
TO SP
D. Acosta, University of Florida
Rx
Rx
Rx
60
27
PIPELINE
PLD
60
10K130E
or
20K200E
CONNECTOR TO
SORTER BOARD
2
1
2
1
21
60
84
TriDAS Review May 2000
20
Summer Plans
Crate test with prototype SR, SP, CCB
(and TMB, MPC) scheduled for summer 2000
• Bench tests start June 1
• Integration tests start July 1
• Will test optical link connections and trigger algorithms
at 40 MHz, verify output and latency
All designs are proceeding well, and we should
be able to make milestone
• Conceptual design, schematics, and some layouts
already exist
Development of test software started
D. Acosta, University of Florida
TriDAS Review May 2000
21
R (cm)
Separation of DT/CSC Coverage
Slow simulation of CMS detector in GEANT 3.21
800
η = 1.04
ME1/3
700
600
500
400
MB2/1
300
200
100
0
0
200
400
600
800
1000
1200
Z (cm)
D. Acosta, University of Florida
TriDAS Review May 2000
• Hard boundary
defined η=1.04
• Separate TrackFinders
optimized for
each system
• Information
shared across
boundary for
maximum
efficiency
• Tentative
agreement
reached on
DT/CSC
interface Feb’00
22
Advantages of Proposal
•
Interconnections are cut in half when track segments
from ME 2/2 and MB 2/2 are not shared
(only ME 1/3 and MB2/1 are shared)
•
The mapping of 60° CSC trigger sectors onto
30° DT ones is avoided (no ME 2/2)
•
But, ME1 station has 30° or 20° subsectors, so there
may still be a mapping problem
•
The RPC data may be used by the GMT to settle any
ghosting problem if a single muon is found by both
Track-Finders
•
φb and η do not need to be sent by the CSC
Track-Finder for DT T-F extrapolations
D. Acosta, University of Florida
TriDAS Review May 2000
23
Advantages Continued
•
The DT Track-Finder may trigger on
MB1-MB2 type tracks
• These track segments and all those sent by
the CSC trigger are assumed to be in barrel
region
•
The CSC Track-Finder logic is considerably
simplified with proposed boundary
• Already assumed in present prototype
D. Acosta, University of Florida
TriDAS Review May 2000
24
Issues with Proposal
Must demonstrate acceptable efficiency
by simulation
CSC Sector Receiver must be designed
to send only 2 track segments (out of 3)
for the barrel-overlap region
D. Acosta, University of Florida
TriDAS Review May 2000
25