Advanced Microprocessors
PS02CINS02
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8086 Microprocessor
• Announced in 1978
• High Performance CMOS (HMOS)
technology
• 29000 Transistors
• 40 pin DIL
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Pin-out Diagram
•
•
•
•
•
•
Supply (GND, GND, VCC)
Clock (CLK,RESET, READY)
Address/Data (AD0-AD15, A16/S3-A19/S6)
Interrupts (NMI,INTR)
Other control (RD’,TEST’,MN/MX’)
Mode Multiplexed
– HOLD---RQ /GT DT/R’----S ’
0
0
1
HLDA---RQ1/GT1 M/IO’---S2’
WR’---LOCK’
ALE---QS0
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DEN’---S
INTA’---QS1
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SYSTEM MODES
• The 8086 can be configured to work in
either of two modes.
– minimum mode
– maximum mode.
• MN/MX’ =1
– Typically smaller and contain single
microprocessor.
• MN/MX’ =0
– Larger systems and with multiple
processors.
– Lets the 8086 meet the needs of a wide
variety ofFree
system
requirements.
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Common Signals
Name
Function
Type
AD7-AD0
Address/data bus
Bidirectional, 3-state
A15-A8
Address bus
Output, 3-state
A19/S6-A16/S3 Address/status
Output, 3-state
MN/MX
Minimum/ maximum Mode control Input
RD
Read control
Output, 3-state
TEST
Wait on test control
Input
READY
Wait state control
Input
RESET
System reset
input
NMI
Non-maskable Interrupt request
input
INTB
Interrup t request
Input
CLK
System clock
input
Vcc
+5V
Input
GND
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Minimum Mode Signals
Name
HOLD
HLDA
WR
IO/M
DT/R
DEN
SSO
ALE
INTA
Function
Hold request
Hold acknowledge
Write control
IO/memory control
Data transmit/receive
Data enable
Status line
Address latch enable
Interrupt acknowledge
Type
Input
Output
Output, 3-state
Output, 3-state
Output, 3-state
Output, 3-state
Output, 3-state
Output
Output
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Maximum Mode Signals
Name
RQ/GT1,0
LOCK
S2-S0
QS1, QS0
Function
Request/grant bus
access control
Bus priority lock
control
Bus cycle status
Instruction queue
status
Type
Bi-directional
Output, 3-state
Output, 3-state
Output
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Minimum Mode System
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Minimum Mode Signals
• AD0-AD15
• A16/S3-A19/S6
• Control Signals
– ALE
– M/IO’
– DT/R’
– BHE
– RD’ & WR’
– DEN
– READY
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Minimum Mode Signals
• Interrupt Signals
– NMI
– INTR
– INTA
– TEST
– WAIT
– RESET
• DMA Signals
– HOLD
– HLDA
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8284 Clock Generator
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8284 Clock Generator
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8284 Clock Generator
• X1,X2 Crystal Inputs
• CLK-(MOS level)->CLK i/p of 8086.
– fCLK = (1/3)fCRYSTAL .
• PCLK and oscillator clock (OSC).
– fPCLK = (1/2)fCRYSTAL
– fOSC = fCRYSTAL
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8284 Clock Generator
• 8284 can also be driven by external clock
source. The external clock is connected to
EFI input.
– F/C = 1 for EFI and F/C=0 for Crystal input
• The CSYNC input is used for external
synchronization in multiple clock system.
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Maximum Mode System
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Maximum Mode Signals
•
•
•
•
• Interrupt Signals
AD0-AD15
– NMI
A16/S3-A19/S6
– INTR
S0,S1,S2
– TEST
Control Signals
– ALE
– BHE
– RD’
– READY
– RESET
• DMA Signals
– RQ/GT0 & RQ/GT1
• LOCK
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8288 Bus Controller
• 8086 does not directly provide all the
signals that are required to control the
memory, I/O, and interrupt interfaces.
• Specifically, the WR, IO/M, DT/R, DEN,
ALE, and INTA signals are no longer
produced by the 8086.
• Instead, it outputs a status code on three
signals lines, So, S1, and S2, prior to the
initiation of each bus cycle.
• This 3-bit bus status code identifies which
type of us cycle is to follow.
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8288 Bus Controller
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8288 Bus Controller
• S2S1S0 are input to the external bus
controller device, the 8288, which
decodes them to identify the type of
MPU bus cycle.
• In response, the bus controller generates
the appropriately timed command and
control signals.
memory read command
(MRDC)
advanced memory write
command (AMWC)
memory write command (MWTC)
advanced I/O write command
(AIOWC)
I/O write command (I0WC)
I/O read command (IORC)
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interrupt
acknowledge
(INTA)
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8288 Bus Controller
Status Inputs
S0 S1 S2
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
CPU Cycle
8288 Command
Interrupt
INTA
Acknowledge
Read I/O Port
IORC
Write I/O Port
lOWC /AIOWC
Halt
None
Instruction Fetch
MRDC
Read Memory
MRDC
Write Memory
MWTC,AMWC
Passive
None
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8288 Bus Controller
• Lock
– To implement a multiprocessor system, a
signal called lock (LOCK) is provided on
the 8086.
– 0 - if the processor wants to lock out the
other processors from using the bus when
a shared resource is accessed.
• RQ/GT0 and RQ/GT1
– In maximum-mode HOLD and HLDA signal
are replaced by RQ/GT0 and RQ/GT1.
They provide a prioritized bus access
mechanism for accessing the local bus.
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8288 Bus Controller
• Queue Status Signals (QS0 and QS1)
– This code tells the external circuitry what
type of information was removed from the
instruction queue during the previous clock
cycle. Figure shows the four different queue
status codes.
01
10
11
The first byte of an instruction was
taken off the queue.
the queue is reset due to a transfer
of control
The fetch of the next byte of the
instruction
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