This module will help you understand how your synthesis tool, the ISE software, HDL coding style, and other factors that affect your ability to meet your system timing objectives
Timing closure is a large topic that encompasses many of the topics we covers in the Essentials of FPGA Design and the Designing for Performance courses
Page 2

After completing this module, you will be able to:
Describe the overall flow for gaining timing closure
Specify the key elements in achieving timing closure
Describe the importance of your HDL coding style
Explain the importance of using Cores in your design
List the most effective implementation options that can help you
Page 3

Every device family has a maximum performance rating that is a measure of your device’s speed
– These performance ratings are “peak” performance = 1 logic level
• Spartan-6 (400 MHz)
• Virtex-6 (650 MHz)
• Virtex-5 (550 MHz)
• Note that these frequencies are based on some of the shortest routing resources (but still easily accessible) being used
– But what is typical? What can I expect?
• That requires a good timing estimate
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Synthesis tools have access to logic delays, but not net delays
– To resolve this, synthesis tools use a loading model as a net delay estimate
• Up to 50% uncertainty
• Xilinx still recommends that you review your synthesis tools timing estimate
Experienced FPGA designers know that another estimate is to use the 50/50 rule
– This assumes that your logic delay (Tilo + Tsu + Tckdi delay) will typically equal an average net delay
• From the Virtex-6 data sheet (using the -3 speed grade, fastest device)
• Tilo = .18ns, Tsu = .29ns, and Tckdi = .30ns
• Tlogic = .77ns and Troute ~ .77ns for an estimate of 1.54ns for 1 logic level (this corresponds to the 650 MHz estimate)
• Likewise, 2 logic level ~3.08ns and 3 logic level ~ 4.62ns
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You must remember …
– A logic level is a clock-to-out on a CLB register, plus a LUT delay, plus a setup time on a CLB register
– Tckdi + Tilo + Tsu
– Your performance is greatly impacted by the number of logic levels
– FPGA experts know if you want to improve your system speed, first make sure you have evaluated the number of logic levels on your timing critical path
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Least experienced customers typically design their worst case path at 3 to 5 logic levels
– Worst case path ~ 7.7ns = 129 MHz
Most experienced customers typically design their worst case path at 2 logic levels
– Worst case path ~ 4.62 = 324 MHz
– But this will depend on the effort you put in to follow good HDL coding techniques and optimize your design for your FPGA architecture
• Replicating logic to reduce high fanout net delays
• Pipeline to reduce logic levels
• Using alternative design techniques to reduce logic levels
• Using your synthesis options to reduce logic levels
• Using advanced implementation options to improve the place and route solution
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The I/O Planner allows you to view both the Die and Package views so that you can understand the I/O pin relationship to I/O banks and dedicated hardware

Placement reviewed in the Device view
– Timing critical nets and logic in green (20% of design)
– Note the green lines correspond to routing to/from I/O pins
• Is there anything wrong?

Basic HDL Coding Techniques Videos
– Synchronous Design methodology
– Finite State Machine design
– Instantiation versus Inference
– Hierarchy management
– Common HDL coding mistakes
Virtex-6 and Spartan-6 HDL Coding Techniques Videos
– Managing device resources
– Control signal usage (clocks, CE, and resets)
– Flip-flop configurations
– Reducing control sets
– Common HDL coding mistakes
– Managing resets
– GSR usage
– Design tips
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Cores are optimized components
– Cores are created by expert designers who have in-depth knowledge of
Xilinx FPGA architecture
• Use the optimum architecture resources so it saves you from instantiating dedicated hardware
 Instantiation of the core is required
– Guaranteed functionality saves time during simulation
Increase design performance
– Cores that contain mapping and placement information have predictable performance that is constant over device size and utilization
– The data sheet for each core provides performance expectations
• Use timing constraints to achieve maximum performance

Without global timing constraints
With global timing constraints

Timing constraints define your timing objectives
– Over-constraining gets you nothing, but costs extra PAR time
– Always use timing constraints, even when your timing objective is modest
– Refer to the Global Timing Constraints REL for more information
Unrealistic constraints will cause the tools to stop
– Your synthesis tool’s timing report and the Post-Map Static Timing Report contain performance estimates
After implementing, review the Post-Place & Route Static Timing
Report to determine if your objectives were met
– If your constraints failed, use the Timing Report to determine the cause
– The Timing Analyzer is introduced in the
Designing for Performance course

The Period constraint defines the maximum allowable internal delay (between two synchronous elements)
The Offset In constraint covers your input pin to synchronous element delay paths
The Offset Out constraint covers your synchronous element to output pin delay paths
Path Specific constraints describe false paths and multi-cycle paths
– All of these timing constraints are necessary
– Global Timing constraints are covered in the Essentials of FPGA Design course (there is also a free REL)
– Path Specific constraints are only covered in the Designing for
Performance course

The easiest way to use advanced synthesis and implementation options
– Pre-assigned options are set into templates
• Balanced (default)
• Timing Performance
• Area Reduction
• Minimum Runtime
• Power Optimization
– You can edit strategies

There are many synthesis options that can help you obtain your performance and area objectives
– Timing-driven synthesis
– FSM extraction
– Retiming
– Register duplication
– Hierarchy management
– Resource sharing
– Physical optimization
Refer to the Synthesis Options Video and the XST Synthesis
Options Video

The implementation tools support several options to help improve your timing results
– Tools automatically stops when all timing constraints are met
– These options do add extra time during place and route
– Options used include
• Overall Effort Level (MAP and PAR)
• Extra Effort Level (MAP and PAR)
• Tools automatically use timing constraints during MAP (-timing)

Constraint summary
– Number of paths analyzed
– Number of timing errors
– Length of critical path
Total delay
– Clock and data breakdown
Clock jitter analysis
Detailed path description
– Delay types are described in the data sheet
– Worst-case conditions are assumed, unless pro-rated

Data Path: source to dest
Delay type Delay(ns) Logical Resource(s)
----------------------------------------------
Tcko 0.290 source net (fanout=7) 0.325 net_1
Tilo 0.060 lut_1 net (fanout=1) 1.500 net_2
Tilo 0.060 lut_2 net (fanout=1) 0.245 net_3
Tilo 0.060
lut_3 net (fanout=1) 0.204 net_4
Tdick 0.300 dest
---------------------------------------------------------
Total 3.044ns (0.770ns logic, 2.274ns route)
(25.3% logic, 74.7% route)
This path is constrained to 3 ns
What is the primary cause of the timing failure?
The Timing Analyzer is covered in the Designing for Performance course

Iterates through the implementation process, trying different combinations of properties
– Automatically stops when all timing constraints are met
– Options used include
• Overall Effort Level (MAP and PAR)
• Extra Effort Level (MAP and PAR)
• Global Optimization (MAP)
• Retiming (MAP)
• Register Duplication (MAP)
• Logic Optimization (MAP)
• Optimization Strategy/Cover Mode (MAP)
• Allow Logic Optimization Across Hierarchy (MAP)

SmartXplorer compares the results of all iterations
Best result is saved to the project directory
– The options used by SmartXplorer to obtain the best results are promoted to the current project options
Information on all iterations is available in the Design
Summary screen

This opens the Multiple Runs
Wizard
– Select from numerous synthesis and implementation option settings for each run
– Specify a directory location to store your results
– Specify a host if you want to run on a workstation
After completion load up each result and compare
This and other PlanAhead features are covered in the
PlanAhead courses

Placement reviewed in the Device view
– Timing critical nets and logic in green (20% of design)
– Note the placement of the yellow CLBs
• Is there anything wrong?

– Boxes are only rough area constraints, in this case
– Note the red lines, they represent the greatest concentration of routes between hierarchical blocks
• Where should each
Pblock go?
3
4
2
1
6
5

Timing Closure is a design activity, not an automatic activity, and not a “push-button” flow
Gaining timing closure requires…
―
Good design knowledge and skills (HDL experience and alternative design techniques)
―
FPGA architecture knowledge
―
Significant tool experience (synthesis, simulation, and implementation)
―
Proper design planning (pin assignments)
Page 27

Xilinx online documents (www.support.xilinx.com)
– Spartan-6 FPGA User Guide
– Virtex-6 FPGA User Guide
Software manuals
– Command Line Tool User Guide
– Timing Constraints User Guide
– Synthesis and Simulation Design Guide
– PlanAhead User Guide
– XST User Guide
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Many FREE Videos are available to help you in many significant ways
– Basic HDL Coding Techniques
– Virtex-6 and Spartan-6 FPGA HDL Coding Techniques
– Synthesis Options
– XST Synthesis Options
– Global Timing Constraints
– Area Constraints…and MORE
All of these Videos are available at no cost at www.xilinx.com/training/free-video-courses.htm

Xilinx Education Services courses
― www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture and other topics (free Videos!)
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