1—Intro Slide
Hello and welcome to this recorded E-Learning about FPGA Power Management
Design Techniques. My name is Frank Nelson. I am a Xilinx technical trainer and course developer. I will be your instructor for this module.
2- Print this REL
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3- Objectives…
(Read slide)
4—Goal: Reduce Power Consumption
To reduce your FPGAs power you have to look for opportunities to reduce the logic in your design. This will allow you to use as small a device as possible and save more static power.
You will also need to use as much of the dedicated hardware resources (such as DSP slice and Block RAM resources) as available. These resources use less power than an equivalent function built with CLB logic. To do this you will need to be comfortable using the Core Generator and instantiating components from either the Xilinx Unified
Library or the Core Generator.
As you will see in a couple slides you will also need to manage your control signal usage.
You will also need to be comfortable using your synthesis tool to infer the optimum resources, and this will require you to be able to verify which resources are used with your synthesis tools schematic viewer.
5—Hard-IP Blocks
You should remember that using the dedicated hard-IP blocks is one of the most powerful ways to lower both your static and dynamic power. They lower static power because total transistor count is lower in the dedicated hardware than it is when building an equivalent component with CLB logic.

6- Use the Smallest Device Possible
These design practices are some of the most useful for reducing the size of your design.
Time slicing allows a circuit to perform less work and use less power. Any time you can time slice your application the more power you will save.
You also should consider using alternative design practices to target unique and common components to extra dedicated hardware resources. In this example, one of the most useful is migrating a required FSM to a block RAM. These design practices take a little extra time, but they are very useful at allowing the user to get the most out of the dedicated hardware, pack more logic into the FPGA, and reduce power.
7- Tactics to Reduce Power
One of the side benefits of reducing the number of LUTs and FFs your design uses is that it also allows you to improve design speed.
You also need to be aware that over-constraining your design during synthesis encourages the synthesis tool to replicate logic.
Designers also need to take special care when they are migrating an existing design to a newer product because the newer products have a more efficient 6-input LUT and older devices had a 4-input LUT. This is important because many FPGA designers have used pipelining to optimize the speed of a data path. If an older design was pipelined it probably has several unnecessary FFs that will actually limit the performance and increase the power necessary. These designs should be repipelined appropriately.
8- Control Signal Problems
Remember that when you instantiate a primitive the port functionality you instantiate is what you are going to get. So if you instantiate a register (or a core that uses a register) make certain that the behavior of that FF is what you want and that you understand the caveats of defining the FFs control ports.
It is important that you understand that the FPGA architecture also dictates what types of control signals can be used. For example, block RAM has a synchronous output register. If you try to infer an asynchronous output, your synthesis tool will not infer the output register. This can affect your device utilization and output performance of the block RAM.
Your synthesis tool can also infer a high fan-out control signal, so be sure to evaluate what you are getting with your synthesis tools schematic viewer.

9- Avoid Active-Low Control Signals
Active-low signals use more LUTs because they require inversion before they can directly drive the control port of a register. This inversion must be done with a LUT and thus takes up a LUT input.
Likewise, because only a single reset can be brought to the register, if the remaining logic to be grouped does not share all common control signals it cannot be grouped into the same slice.
If you use any hierarchical design techniques (meaning you are using partitions, or keep hierarchy, using cores, using multiple netlists, and using bottom-up synthesis), it can increase the number of control signals because the flip-flops do not have a programmable inverter.
With hierarchical design, each signal would have a different name, and you would still have to run each signal through an inverter, which means that you are burning a
LUT.
10- Use Active-High Control Signals
This example shows that when you use Hierarchical design methodologies the synthesis tools and the implementation tools cannot merge this logic into the same slice. This is because the designer is not allowing optimization across a hierarchical boundary. This would not happen if the designer had planned on sharing control signals across the design.
11- Design Tips
<read slide>
12- Minimizing the Use of DCMs and PLLs
Be careful when you are migrating designs to a different architecture or merging designs into one device. In this case, the design had an embedded DCM in a lowerlevel block and if the designer did not evaluate their design they would now have two instances of the same block. In every design, the DCM and PLL power consumption is considerable, so this really adds up. So pull those DCMs and PLLs out to the top level so they are not replicated by your synthesis tool.
13- Reducing Clock and Block Activity
You should also take full advantage of the BUFGMUX, BUFCE, and the BUFHCE to gate an entire clock domain for power reduction. This can be done to pause the clock in an entire clock region. Likewise, for applications that only pause the clock on small areas of the design, use the clock enable pin of the FPGA register.

14- Summary
In summary, <read slide>
15- Where Can I Learn More?
Well, there are lots of places to learn more about FPGA Power consumption, and they all start at support.xilinx.com.
<read slide>
16- Where Can I Learn More?
If you would like to see what other courses we offer, or what other Free RELs are available go to the Xilinx Education link you see here.
<read slide>
But whatever you do, please take a second and let us know what you thought of this
REL. Just click on this icon at the top of this page and tell us what you think.
My name is Frank Nelson. You have been listening to the “What are Power
Management Design Techniques?” REL. Thank you for listening and thanks for your business.
17- Legal Stuff
<nothing said>