Timing Closure
© 2010 Copyright Xilinx
Welcome
 This module will help you understand how your synthesis
tool, the ISE software, HDL coding style, and other factors
that affect your ability to meet your system timing objectives
 Timing closure is a large topic that encompasses many of
the topics we covers in the Essentials of FPGA Design and
the Designing for Performance courses
Page 2
Timing Closure REL
© Copyright 2010 Xilinx
After completing this module,
you will able to:
 Describe the overall flow for gaining timing closure
 Specify the key elements in achieving timing closure
 Describe the importance of your HDL coding style
 Explain the importance of using Cores in your design
 List the most effective implementation options that can help you
Page 3
Timing Closure REL
© Copyright 2010 Xilinx
Timing Closure
Timing Closure REL
© Copyright 2010 Xilinx
Setting Your Performance Expectation
 Every device family has a maximum performance rating that is a
measure of your device’s speed
– These performance ratings are “peak” performance = 1 logic
level
• Spartan-6 (400 MHz)
• Virtex-6 (650 MHz)
• Virtex-5 (550 MHz)
• Note that these frequencies are based on some of the
shortest routing resources (but still easily accessible)
being used
– But what is typical? What can I expect?
• That requires a good timing estimate
Page 5
Timing Closure REL
© Copyright 2010 Xilinx
Performance Estimates
 Synthesis tools have access to logic delays, but not net delays
– To resolve this, synthesis tools use a loading model as a net delay
estimate
• Up to 50% uncertainty
• Xilinx still recommends that you review your synthesis tools timing estimate
 Experienced FPGA designers know that another estimate is to use the
50/50 rule
– This assumes that your logic delay (Tilo + Tsu + Tckdi delay) will
typically equal an average net delay
• From the Virtex-6 data sheet (using the -3 speed grade, fastest device)
• Tilo = .18ns, Tsu = .29ns, and Tckdi = .30ns
• Tlogic = .77ns and Troute ~ .77ns for an estimate of 1.54ns for 1 logic
level (this corresponds to the 650 MHz estimate)
• Likewise, 2 logic level ~3.08ns and 3 logic level ~ 4.62ns
Page 6
Timing Closure REL
© Copyright 2010 Xilinx
Performance Estimates
 You must remember…
– A logic level is a clock-to-out on a CLB register, plus a LUT delay, plus
a setup time on a CLB register
– Tckdi + Tilo + Tsu
– Your performance is greatly impacted by the number of logic levels
– FPGA experts know if you want to improve your system speed,
first make sure you have evaluated the number of logic levels on
your timing critical path
Page 7
Timing Closure REL
© Copyright 2010 Xilinx
Performance Estimates
 Least experienced customers typically design their worst case path at 3
to 5 logic levels
– Worst case path ~ 7.7ns = 129 MHz
 Most experienced customers typically design their worst case path at 2
logic levels
– Worst case path ~ 4.62 = 324 MHz
– But this will depend on the effort you put in to follow good HDL coding
techniques and optimize your design for your FPGA architecture
• Replicating logic to reduce high fanout net delays
• Pipeline to reduce logic levels
• Using alternative design techniques to reduce logic levels
• Using your synthesis options to reduce logic levels
• Using advanced implementation options to improve the place and route solution
Page 8
Timing Closure REL
© Copyright 2010 Xilinx
Pin Planning
 The I/O Planner allows you to view both the Die and Package
views so that you can understand the I/O pin relationship to I/O
banks and dedicated hardware
Timing Closure REL
© Copyright 2010 Xilinx
Pin Planning Case Study
 Placement reviewed
in the Device view
– Timing critical nets and
logic in green (20% of
design)
– Note the green lines
correspond to routing
to/from I/O pins
• Is there anything
wrong?
Timing Closure REL
© Copyright 2010 Xilinx
HDL Coding Techniques
 Basic HDL Coding Techniques RELs
– Synchronous Design methodology
– Finite State Machine design
– Instantiation versus Inference
– Hierarchy management
– Common HDL coding mistakes
 Virtex-6 and Spartan-6 HDL Coding Techniques RELs
– Managing device resources
– Control signal usage (clocks, CE, and resets)
– Flip-flop configurations
– Reducing control sets
– Common HDL coding mistakes
– Managing resets
– GSR usage
– Design tips
Page 11
Timing Closure REL
© Copyright 2010 Xilinx
Using the Core Generator
 Cores are optimized components
– Cores are created by expert designers who have in-depth knowledge
of Xilinx FPGA architecture
• Use the optimum architecture resources so it saves you from instantiating
dedicated hardware
 Instantiation of the core is required
– Guaranteed functionality saves time during simulation
 Increase design performance
– Cores that contain mapping and placement information have
predictable performance that is constant over device size and
utilization
– The data sheet for each core provides performance expectations
• Use timing constraints to achieve maximum performance
Timing Closure REL
© Copyright 2010 Xilinx
Logic Placement Can Be Very Different with
Timing Constraints
 Without global timing constraints
Timing Closure REL
 With global timing constraints
© Copyright 2010 Xilinx
Timing Constraints Define Your Performance
Objectives
 Timing constraints define your timing objectives
– Over-constraining gets you nothing, but costs extra PAR time
– Always use timing constraints, even when your timing objective is
modest
– Refer to the Global Timing Constraints REL for more information
 Unrealistic constraints will cause the tools to stop
– Your synthesis tool’s timing report and the Post-Map Static Timing
Report contain performance estimates
 After implementing, review the Post-Place & Route Static
Timing Report to determine if your objectives were met
– If your constraints failed, use the Timing Report to determine the
cause
– The Timing Analyzer is introduced in the Designing for Performance
course
Timing Closure REL
© Copyright 2010 Xilinx
Timing Constraints
 The Period constraint defines the maximum allowable
internal delay (between two synchronous elements)
 The Offset In constraint covers your input pin to
synchronous element delay paths
 The Offset Out constraint covers your synchronous element
to output pin delay paths
 Path Specific constraints describe false paths and multicycle paths
– All of these timing constraints are necessary
– Global Timing constraints are covered in the Essentials of FPGA
Design course (there is also a free REL)
– Path Specific constraints are only covered in the Designing for
Performance course
Timing Closure REL
© Copyright 2010 Xilinx
Design Goals & Strategies
 The easiest way to use advanced
synthesis and implementation
options
– Pre-assigned options are set into
templates
• Balanced (default)
• Timing Performance
• Area Reduction
• Minimum Runtime
• Power Optimization
– You can edit strategies
Timing Closure REL
© Copyright 2010 Xilinx
Synthesis Options
 There are many synthesis options that can help you obtain
your performance and area objectives
– Timing-driven synthesis
– FSM extraction
– Retiming
– Register duplication
– Hierarchy management
– Resource sharing
– Physical optimization
 Refer to the Synthesis Options REL and the XST Synthesis
Options REL
Timing Closure REL
© Copyright 2010 Xilinx
Implementation Options
 The implementation tools support several options to help
improve your timing results
– Tools automatically stops when all timing constraints are met
– These options do add extra time during place and route
– Options used include
• Overall Effort Level (MAP and PAR)
• Extra Effort Level (MAP and PAR)
• Tools automatically use timing constraints during MAP (-timing)
Timing Closure REL
© Copyright 2010 Xilinx
Locating Timing Critical Paths (Timing Analyzer)
 Constraint summary
– Number of paths analyzed
– Number of timing errors
– Length of critical path
 Total delay
– Clock and data breakdown
 Clock jitter analysis
 Detailed path
description
– Delay types are described in
the data sheet
– Worst-case conditions are
assumed, unless pro-rated
Timing Closure REL
© Copyright 2010 Xilinx
Case 1
Data Path: source to dest
Delay type
Delay(ns)
---------------------------Tcko
0.290
net (fanout=7)
0.325
Tilo
0.060
net (fanout=1)
1.500
Tilo
0.060
net (fanout=1)
0.245
Tilo
0.060
net (fanout=1)
0.204
Tdick
0.300
---------------------------Total
3.044ns
Logical Resource(s)
------------------source
net_1
lut_1
net_2
lut_2
net_3
lut_3
net_4
dest
-----------------------------(0.770ns logic, 2.274ns route)
(25.3% logic, 74.7% route)
 This path is constrained to 3 ns
 What is the primary cause of the timing failure?
 The Timing Analyzer is covered in the Designing for Performance
course
Timing Closure REL
© Copyright 2010 Xilinx
SmartXplorer
 Iterates through the implementation process, trying different
combinations of properties
– Automatically stops when all timing constraints are met
– Options used include
• Overall Effort Level (MAP and PAR)
• Extra Effort Level (MAP and PAR)
• Global Optimization (MAP)
• Retiming (MAP)
• Register Duplication (MAP)
• Logic Optimization (MAP)
• Optimization Strategy/Cover Mode (MAP)
• Allow Logic Optimization Across Hierarchy (MAP)
Timing Closure REL
© Copyright 2010 Xilinx
SmartXplorer Results
 SmartXplorer compares the results of all iterations
 Best result is saved to the project directory
– The options used by SmartXplorer to obtain the best results are
promoted to the current project options
 Information on all iterations is available in the Design
Summary screen
Timing Closure REL
© Copyright 2010 Xilinx
Multiple Runs (XploreAhead) with PlanAhead
 This opens the Multiple Runs
Wizard
– Select from numerous synthesis
and implementation option
settings for each run
– Specify a directory location to
store your results
– Specify a host if you want to run
on a workstation
 After completion load up each
result and compare
 This and other PlanAhead
features are covered in the
PlanAhead courses
Timing Closure REL
© Copyright 2010 Xilinx
Area Constraints
 Placement reviewed
in the Device view
– Timing critical nets and
logic in green (20% of
design)
– Note the placement of
the yellow CLBs
• Is there anything
wrong?
Timing Closure REL
© Copyright 2010 Xilinx
Area Constraints
 Top-level floorplan
(this is just Pblocks
with no area
constraints)
3
4
– Boxes are only rough
area constraints, in this
case
2
– Note the red lines, they
represent the greatest
concentration of routes
between hierarchical
blocks
1
• Where should each
Pblock go?
Timing Closure REL
5
© Copyright 2010 Xilinx
6
Timing Closure
Timing Closure REL
© Copyright 2010 Xilinx
Summary
 Timing Closure is a design activity, not an automatic activity,
and not a “push-button” flow
 Gaining timing closure requires…
―Good design knowledge and skills (HDL experience and
alternative design techniques)
―FPGA architecture knowledge
―Significant tool experience (synthesis, simulation, and
implementation)
―Proper design planning (pin assignments)
Page 27
Timing Closure REL
© Copyright 2010 Xilinx
Where Can I Learn More?
 Xilinx online documents (www.support.xilinx.com)
– Spartan-6 FPGA User Guide
– Virtex-6 FPGA User Guide
 Software manuals
– Command Line Tool User Guide
– Timing Constraints User Guide
– Synthesis and Simulation Design Guide
– PlanAhead User Guide
– XST User Guide
Page 28
Timing Closure REL
© Copyright 2010 Xilinx
Recommended REL Modules
 Many FREE RELs are available to help you in many
significant ways
– Basic HDL Coding Techniques
– Virtex-6 and Spartan-6 FPGA HDL Coding Techniques
– Synthesis Options
– XST Synthesis Options
– Global Timing Constraints
– Area Constraints…and MORE
 All of these RELs are available at no cost at
www.xilinx.com/training/free-video-courses.htm
Timing Closure REL
© Copyright 2010 Xilinx
Where Can I Learn More?
 Xilinx Training
―www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture and other topics (free training videos!)
Page 30
Timing Closure REL
© Copyright 2010 Xilinx
Trademark Information
Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on,
or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded,
displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or
otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT
THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You
represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.
Page 31
Timing Closure REL
© Copyright 2010 Xilinx