MYTHREYI NETHI
950 E Hillsdale Blvd
Apt # 204, Foster City
CA 94404-2111
Email: mnethi@siue.edu
Home: (650) 522-9792
Mobile: (650) 218-4020
Website: www.siue.edu/~mnethi
Objective:
A career in design, verification and implementation of the next generation high performance VLSI,
ASIC, digital and analog designs, where I can utilize best of my knowledge and research experience.
Areas of Interest:
Circuit design, logic design, system modeling using VHDL and Verilog HDL, analog circuit design,
computer architecture.
Technical Summary:
 Over 2 and ½ years of experience as an ASIC Designer.
 Good in designing and implementing analog and digital circuits.
 Strong in hardware descriptive languages like Verilog, VHDL, VerilogA.
 Hands-on experience in FPGA design tools, Mentor Graphics and Cadence tools.
 Proven experience in large tapeouts which has 500,000 gates (3 version chips already taped out and
are working great).
 Good expertise in scripting languages like Perl, Eldo scripting, Ocean and Skill scripting.
 Strong in programming languages and packages like C, Visual Basic 6.0, Matlab.
 Excellent programming and debugging skills.
 Fluent using Matlab and C for simulation.
 Worked in Unix, Solaris, HP-UX, Windows NT, and Windows 2000/XP environments.
 Excellent verbal and written skills.
 Excellent inter-personnel, communication and team player skills.
Experience:
 Research Associate (Jan 2003 – Sep 2003), Research Assistant (May 2001 - Dec 2002)
VLSI Design Laboratory,
Southern Illinois University Edwardsville.
Research Project: An integrated circuit is needed for high density signal processing in low and
intermediate energy nuclear physics community. The IC is designed for use with an array of silicon
strip detectors in a wide variety of colliding particle experiments. It is fabricated in the AMI 0.5 um,
N-well, double-poly, triple-metal, high-resistance C5N process through MOSIS. Three versions of
this chip were fabricated till date. The fourth generation IC designed was sent for fabrication in July
2003. The die size is 6mm x 3mm and the transistor count is 500,000. A manuscript of the entire
research work is available at www.siue.edu/~mnethi.
Major blocks that were designed in this research are:
 Charge sensitive amplifier.
 Pulse shaper.
 Peak sampler circuit.
 Constant fraction discriminator.
 Leading edge discriminator.
 Digital-to-analog converter.
 Zero cross discriminator
 Time-to-voltage converter.
 Bias generators.
 Readout electronics.
Responsibilities:
 Designing of circuits both analog and digital.
 Performing timing analysis, noise analysis (analog), transient analysis (analog, digital and
mixed mode)
 Writing test bench in Verilog and VHDL.
 Full custom layout of the entire design.
 Performing post layout simulations.
 Extracting GDSII for tapeout.
 Teaching Assistant (Aug 2001 - May 2002)
Department of Electrical Engineering,
Southern Illinois University Edwardsville.
Duties included instructing students in laboratory, helping students with course projects, and
assisting students in running SPICE simulations; all for a junior- level analog electronics course (first
course in a two-course sequence).
Publications:
“A Multi-Channel Integrated Circuit for Use in Low and Intermediate Energy Nuclear Physics
HINP32C” George L. Engel, Muthukumar Sadasivam, Mythreyi Nethi, Jon Elson, Lee Sobotka,
Robert Charity (In preparation for the journal “Nuclear Instruments and Methods in Physics
Research”).
Master's Project:
“FPGA implementation of a fast pipelined Floating Point Unit (FPU) using Verilog® HDL.”
The FPU is fully IEEE 754 compliant. All four rounding modes and exceptions are implemented.
Booth Wallace multiplier and SRT radix-4 divider are implemented. The execution and rounding
stages are implemented in parallel thus reducing the number of stages in pipeline and increasing the
operating frequency. It was implemented on Xilinx Virtex XSV300-pq240 FPGA.
Other Projects:
 Design, simulation and full Custom layout of a 16-bit ALU targeting American Microsystem's
(AMI) 0.5µm process.
This project involved the design of 16-bit ALU. Mentor Graphics Design Architect was used for
schematics and Accusim was used to simulate the design. The full custom layout was targeted for
AMI 0.5m process. The layout involved Floor Planning and is layed out using IC station
 Design and implementation of a 16-bit simple micro-processor using VHDL.
This project involved Modeling of a 16 bit (40 instructions) processor in VHDL. The processor was
simulated using Modelsim and was synthesized with Mentor Graphics Leonardo Spectrum. This
project was implemented on a Xilinx FPGA targeting Virtex parts library.
 Modeling of a cache controller using Verilog.
The cache controller was modeled in Verilog and was synthesized using Leonardo spectrum. The
cache controller generated write hit, write miss, read hit, read miss signals based on which wait
states were introduced in the instruction cycle of the microprocessor.
 Design, simulation and noise analysis of a folded cascode operational transconductance amplifier
(OTA).
This project involved in design of folded cascade OTA that is commonly used in switched capacitor
circuits. Simulations and noise analysis are done using Eldo scripting and Xelga.
 Design and implementation of a 3-bit flash Analog-to-Digital Converter using Cadence tools.
 Modeling of low energy nuclear physics experimental circuits using Verilog-A.
 Developed specialized application software for modern scientific data acquisition system (Keithley
236 Source/Measure Unit) using a GPIB Interface in Visual Basic.
Languages:
VHDL, Verilog® HDL, VerilogA, Perl, 8085 assembly language programming, C.
CAD Tools:
Mentor Graphics: Design Architect, IC Station, Renoir, Eldo (SPICE simulator), Leonardo
Spectrum, Quicksim, Accusim (SPICE simulator), Lsim, Modelsim, Advance MS (mixed-signal
analyzer).
Cadence: ORCAD Schematic Capture, PSPICE, Virtuoso composer, Virtuoso-XL layout editor,
Ambit, Verilog-XL, Affirma, Spectre (SPICE simulator), Spectre-Verilog (mixed-signal analyzer),
Silicon Ensemble, Ocean and Skill scripting.
Packages:
Mat lab, Visual Basic 6.0.
Operating Systems: HP-UX, Sun Solaris, Windows 2000/XP.
Education:
Southern Illinois University Edwardsville, IL.
M.S. in Electrical and Computer Engineering. (GPA - 3.8/4.0)
Nagarjuna University, India.
B.Tech in Electrical and Electronics Engineering. (GPA - 3.9/4.0)
Graduate Courses: Digital CMOS VLSI Design, Analog CMOS VLSI Design, Computer System Architecture, High
Performance Architectures, Discrete-Time Signal Processing, Advanced Instrumentation, Computer
Networks, Advanced Stochastic Processes.
Awards and Honors: Graduate research and teaching assistantship in the department of Electrical & Computer Engineering.
Memberships:
Student member in IEEE.
References:
Dr. George L. Engel, Associate professor in Electrical Engineering, Southern Illinois University.
Dr. Scott R. Smith, Associate Professor in Electrical Engineering, Southern Illinois University.
Dr. Lee G. Sobotka, Professor in Department of Chemistry, Washington University in St.Louis.