A Verilog Model of Universal Scalable Binary
Sequence Detector
ABSTRACT
This paper presents a Verilog based Universal Sequence Detector, which will be able to
detect a binary sequence, from a sequence of inputs. The Sequence Detector looks for some
specified sequence of inputs and outputs 1, whenever the desired sequence has found. The
sequence detector is like a lock which unlocks (outputs 1), only when a combination appears.
Coding of design is done in Verilog HDL and the design is tested and simulated in ModelSim
Simulator and is implemented on Xilinx.
LANGUAGE USED:
 Verilog
TOOLS REQUIRED:
 MODELSIM – Simulation
 XILINX-ISE – Synthesis