Tutorial 1
An Introduction to Verilog:
Transitioning from VHDL
Lesson Plan (Tentative)
• Week 1: Transitioning from VHDL to
Verilog, Introduction to Cryptography
• Week 2: A5 Cipher Implementaion,
Transitioning from Verilog to Verilog-A
• Week 3: Verilog-A Mixer Analysis
Purpose of HDL Languages
• Simplify design so you can concentrate on
the overall picture
• HDL allows description in language rather
than schematic, speeding up development
time
• Allows reuse of components (standard
cells ie libraries)
VHDL/Verilog Differences
• Verilog modelled after C, VHDL is modelled after
Ada
– VHDL is more strongly typed (ie it checks the typing
more rigorously)
– Verilog is case sensitive while VHDL is not
• This means that VHDL has a higher learning
curve than Verilog, but with proficiency, offers
more flexibility.
• Verilog used extensively in the US while VHDL is
used internationally
Verilog Types
• wire, wire[msb:lsb] (single/multiple bit wire)
• reg, reg[msb:lsb] (single/multiple bit
register)
• integer (integer type, 32 bits)
• time (unsigned 64 bit)
• real (floating point double)
• string
Operators
Arithmetic:
• Binary +, -, *, /, % (mod)
• Unary +, - (sign)
Relational
• Binary <, >, <=, >=
Operators (con’t)
Equivalence Operators
• === (equivalence including x and z), ==,
!== (again including x and z), !=
Bit-wise Operators
• ~ (not), & (and), | (or), ^ (xor), ~^, ^~ (xnor)
Operators (con’t)
•
•
•
•
Shift Operators <<, >>
Cocatenation {a, b, c}
Replication {n{m}} (m n times)
Conditional
cond_exp ? True_exp : false_exp
Built in gates
• Can be used without having to build
• and, nand, or, nor, xor, xnor (n-input
gates), used as:
and (out, in1, in2, in3, …)
• buf, bufif1, bufif0, not, notif1, notif0
(transmission gates/tristates)
Entity Instantiation
• No equivalent of architecture keyword in Verilog (all is
treated as one architecture)
VHDL:
Verilog:
entity myentity is
port ( a, b : in std_logic;
c : out std_logic);
end myentity;
Architecture implementation of myentity
--do stuff
end implementation;
module myentity (a, b, c);
input a, b;
output c;
wire a, b, c;
//do stuff
endmodule
Component Instantiation
• Verilog doesn’t require explicit instantiation
VHDL: component DFF
port( d : in std_logic;
q : out std_logic);
end component;
MyDff : DFF
Port map (foo, bar); --implicit
Port map (d => foo, q => bar);--explicit
Verilog:
dff u0 (foo, bar); //implicit
dff u0 (.foo(d), .bar(q)); //explicit
Combinational Assignment
• Note that gate level primitives in Verilog can be a
function or bitwise symbol
VHDL:
Verilog:
a <= b;
a <= b AND c;
a <= b + c;
a <= b;
and(a, b, c);
a <= b & c;
{carry, sum} <= b
//parallel assignment
//a is output
//same as line above
+ c; //carry is
//optional
Flow Logic (I): Case
• Differentiation in VHDL for select statements and
conditional assignment; none in Verilog
VHDL: With std_logic_vector’(A) select
Q
<= “1” when “0”
<= “0” when “1”
<= “0” when others;
• VHDL can also use case statements similar to Verilog
Verilog:
case (A)
0 : Q <= 1;
1 : Q <= 0;
default : Q <= 0;
endcase
Flow Logic (II): If/Then/Else
• Equivalence operators similar to C in Verilog
VHDL:
Q <= ‘1’ when A = ‘1’ else
‘0’ when B = ‘1’ else
‘0’;
Verilog: if (A == 1) begin
Q <= 1;
end else if (B == 1) begin
Q <= 0;
end else begin
Q <= 0;
end
Combinational Processes
VHDL:
Verilog:
process (a)
begin
b <= a;
end process;
always @ (a)
begin
b <= a;
end
Sequential Logic
• Example: D Flip Flop: (note edge triggering is in
always statement in Verilog)
VHDL: process(clk)
begin
if rising_edge(clk)
q <= d;
end if;
End process;
Verilog:
always @ (posedge clk)
begin
q <= d;
end
Test Benches
• Useful for simulation and verification
• Keyword “initial begin .. end” starts a
testbench
– Remember “always begin .. end”
• #delay is used to delay by delay ‘time
units’
• $display(“Random text”) displays Random
text
• `timescale sets the ‘time unit’ unit
Test Benches
• $monitor (“Clk %b, Reg %d”, clk, reg)
displays clock and register variables as
binary and decimal respectively
• #delay $finish runs the testbench for delay
‘time units’
4-bit Counter Code
//Asynchronous Reset 4-bit
//Counter
module counter (clk, reset,
enable, count);
input clk, reset, enable;
wire clk, reset, enable;
output count;
reg[3:0] count;
always @ (reset) //change to
//posedge clk for sync reset
begin
if (reset == 1) begin
count <= 0;
end
end
always @ (posedge clk)
begin
if (enable == 1) begin
count <= count + 1;
end
end
endmodule
Testbench for Counter
• Example:
`timescale 1ns/1ns
module counter_tb;
reg clk, reset, enable;
wire [3:0] count;
counter U0 ( .clk (clk), .reset
(reset), .enable (enable), .count
(count) );
initial begin
clk = 0;
reset = 0;
enable = 0;
end
initial begin
$dumpfile ( "counter.vcd" );
$dumpvars;
end
initial begin
$display(
"\t\ttime,\tclk,\treset,\tenable,
\tcount" );
$monitor(
"%d,\t%b,\t%b,\t%b,\t%d" ,$time,
clk,reset,enable,count);
end
initial
#100 $finish; //ends after 100 ns
endmodule
always
#5 clk = !clk; //flip clock every 5
ns
Tutorial 1 Part 2
Introduction to Cryptography
Cryptography is Everywhere
• Internet (online banking, e-commerce
sites)
• Cell phones (GSM and CDMA)
• Other wireless devices (PDAs and laptops
with wireless cards)
• RFIDs, sensors
Why Hardware Design is important
in Cryptography
• Many cryptographic applications are
hardware-based (cell phones, RFID,
wireless router technology, electronic key
dongles)
• Importance of hardware design knowledge
to efficiently implement applications in
cryptography
Scenario
O
A
B
A wants to communicate with B, however O
can listen in on the conversation. How to
prevent this?
Types of Cryptographic Ciphers
• A cipher is a way of making messages
unreadable
• Two main categories: public key and
private/symmetric key
• Public key uses different keys for encryption and
decryption (which means not having to
exchange keys in person), but is computationally
expensive
• Symmetric key uses the same key for encryption
and decryption, but is relatively cheap in terms
of computation power
Types of Cryptographic Ciphers
• Examples of Public Key Cryptography:
RSA, Diffie-Hellman key exchange, ECC
(Elliptic Curve Cryptography)
• Examples of Symmetric Key
Cryptography: RC4 (used in WEP), A5
(used in GSM), DES and Triple-DES (used
in banking applications)
Linear Feedback Shift Registers
(LFSRs)
• Used in many stream ciphers (a subset of
symmetric key ciphers that outputs 1 bit at
a time; they’re quick, but less secure than
block ciphers)
• Consists of a chain of D Flip Flops and a
set of XORs that feed later bits back into
the beginning
Example
Practical Example of a cipher: A5
• Used in GSM communications as an encryption
scheme
• Consists of 3 LFSRs combined to produce a
single stream of bits
• Details were kept secret; people reverseengineered the cipher to produce the structure
• There have been many attacks since it was
reverse engineered and is now considered
broken
Diagram of A5-1
Summary
• Cryptography is used in many everyday
applications
• Hardware knowledge important to
implement efficient ciphers
• LFSRs important to implement stream
ciphers
• A5-1 (GSM) an application of LFSRs