UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
HW #4: Capacitance, Power, Process Scaling
NTU IC541CA (Fall 2001)
1
Adiabatic capacitor charging

in
a) Standard CMOS
V = VDD
V = 0
out
CL
b) Two-step in Part (b)
V = 0
V
VDD
VDD/2

0
t
Figure 1: Inverter with Variable Power Rails
Recall that the power consumption of an inverter has two principle components: static power dissipation
and dynamic power dissipation. Adiabatic switching is one approach to mitigate these losses. This is
accomplished by changing the voltage on the power and ground rails, instead of keeping them constant
like in ordinary CMOS logic. Assume CL >> CINT (ie. intrinsic capacitance is negligible).
1A
Consider the transient response of a standard CMOS inverter as shown in Figure 1a (with
constant rails at VDD and 0) and external load CL. Assuming sufficient time for the load
capacitance to fully charge/discharge between transitions, how much energy is consumed
charging the load for a pull-up (low to high) transition. How much energy is consumed for a
pull-down (high to low) transition?
After a pull-up transition, how much energy is stored on the capacitor? Why is this different from
the total energy consumed to charge the capacitor?
1B
Now, let’s see what happens if the power is applied in two steps during a pull-up transition, as
shown in Figure 1b. Assume that in = 0 and that there is plenty of time between the steps for the
capacitor to charge up. How much energy does it take to charge the capacitor all the way up to
VDD using this two-step approach?
Derive a simple expression for N steps and make a statement about the energy required as N
approaches infinity.
1C
In theory, an infinite amount of time is required for a capacitor to fully charge up through a
resistance. Clearly, this is too long to wait in a real circuit, so the charging time will be defined
as the time it takes for the capacitor to charge up another 90%. This means, start at the current
voltage and charge up 90% of the voltage difference (it is defined this way to make the general
equation tractable). Assuming the effective resistance of an ‘ON’ transistor is R, consider again
the two-step charging technique used in Part 1B. How long does it take to charge the capacitor
from 0 to 0.9*(VDD/2)? From there (after applying the second step), how long does it take to
charge up another 90%? What is the voltage across the capacitor at this point?
Derive a simple expression, as a function of the number of steps N, for the time it takes to charge
the capacitor, assuming the capacitor is charged 90% more at each step. Call this the propagation
delay of this inverter.
1D
Multiply the delay equation for N steps derived in Part 1C and the energy equation for N steps
derived in Part 1B for a crude energy-delay product. What is the energy delay product as N
approaches infinity? Why is the energy-delay product for N=1 different than that of a standard
CMOS inverter (neglecting short circuit current and static dissipation)?
V
Vdd
Vdd/2
0
T
t
V
Vdd/2
0
T
t
Figure 2: Supply waveforms for adiabatic switching
1E
A set of power waveforms for an adiabatic computer is shown in Figure 2. At t=0, both  and –
are at VDD/2. During this condition, the input is applied. After it is stable, the supply rails slowly
move toward VDD and ground, approximating adiabatic switching with an infinite number of
steps. Once they reach the rails, the output is valid. Before a new input can be applied, the
supplies must slowly be returned to VDD/2.
How does the static power consumption of this device differ from a standard CMOS inverter?
What about short-circuit current?
As an interesting aside, the charge could be saved somewhere else when the load capacitance is
discharged. Since the charge was saved, a switch could be thrown and everything could run backwards to
restore the charge to its original configuration. In this way, the computer consumes almost no energy, and
this is the fundamental premise behind ‘reversible computers’.
2
Process Scaling
A state-of-the-art, synthesizable, embedded microprocessor from a company in the valley consumes
0.4mW/MHz when fabricated using a 0.18 m process. With typical standard cells (gates), the area of the
processor is 0.7 mm2. Assuming a 100 Mhz clock frequency, and 1.8 V power supply. Assume short
channel devices, but ignore second order effects like mobility degradation, series resistance, etc.
2A
Using fixed voltage scaling and constant frequency, what will the area, power consumption, and
power density of the same processor be, if scaled to 0.12 m technology, assuming the same
clock frequency?
If the supply voltage in the scaled 0.12 m part is reduced to 1.5 V what will the power
consumption and power density be?
How fast could the scaled processor in 2B be clocked? What would the power and power density
be at this new clock frequency?
Power density is important for cooling the chip and packaging. What would the supply voltage
have to be for the chip in 2C to maintain the same power density as the original processor?
2B
2C
2D
3
Propagation Delay and Power
VDD = 2.5 V
in
out
...
buffer
receiver
Transistor parameters
 = 0 V-1
VDSATn = 1 V, VDSATp = -1 V
VTn = 0.7, VTp = -0.7 V
k'n = 100 A/V2
k’p = -50 A/V2
L = 0.25 m
Inverter parameters
For (Wp= 0.5 m, Wn= 0.25 m)
CINT = 3 fF
CIN = 3 fF
Figure 3: Calculation model for a 32-bit register select signal
Consider a select signal for a 32-bit register, modeled as an inverter driving 32 minimum sized inverters
as shown in Figure 3. The 32 receiver inverters are fixed at the minimum size. Define propagation delay
of this circuit to be the delay from in to out. Define the size of an inverter to be the width of the NMOS
transistor. Assume that the intrinsic capacitance (CINT) and input capacitance (CIN) of the inverter scale
linearly with transistor width, assuming (Wp = 2*Wn). You may use Req = (3/4) * (VDD/IDSAT)
3A
3B
3C
3D
If the buffer inverter can be scaled for more drive strength, what is the absolute best propagation
delay that can be achieved, assuming a sharp input transition? What size should the driver be to
achieve this propagation delay?
If you have the correct answer for Part 3A, this size is obviously too large. What size should the
buffer be to get 10% worse than the optimum propagation delay?
What buffer size minimizes energy consumption?
If another minimum sized inverter must drive the input to the buffer, calculate what size the
buffer should be to minimize propagation delay (delay from in to out).