Lab 2: The CMOS Inverter This lab shows the basic layout and electrical characteristics of the CMOS inverter which is the fundamental component of integrated MOS logic circuits. 1 Get a copy of the hand-out, Design of a CMOS Inverter. The instructions in this hand-out are from an older version of the microwind manual and for a previous version of microwind. Some of the instruction details may be slightly different for the current version of microwind. Set the FOUNDRY to cmos025.rul. 2 Follow the manual layout design process to produce a CMOS. Use the cell library to add the metal contacts (but not the transistors). As you layout your circuit, check periodically that it meets the design rules by using the drc button. Following these rules ensures that when a circuit is fabricated it will actually work, i.e. it is manufacturable. 3 Attempt to simulate the characteristics as described in the Analog Simulation section. It is likely that a warning signal will appear in information line at the bottom of the screen saying that the a well is floating. It is necessary in CMOS circuits for the n-well to be connected to Vdd by means of an n-type diffusion and a metal contact and also for the p-type substrate to be connected to Vss by means of a p-type diffusion and a metal contact. This ensures that the different areas of silicon where the transistors are made are held at a defined potential in order that the transistors will operate properly. Place these connections in the layout and re-simulate. 4 What are the output rise and fall delays for the circuit you have designed? 5 By using the Voltages and Currents facility in the simulation window, determine the maximum current flowing in the circuit during switching. At what point in the switching cycle does this maximum occur? 6 By using the Voltage vs. Voltage facility, estimate the logic threshold voltage. (The logic threshold voltage is the point where the input and output voltages of the inverter are the same; i.e. the point where it can be said to have switched from ‘ON’ to ‘OFF’ or vice versa.) 7 Record also the inverter ratio; i.e. ratio between the length/width ratio of the pull-up (pMOS) transistor and the length/width ratio of the pull-down (nMOS) transistor. 8 Change the inverter ratio and repeat section (7). How does the logic threshold voltage vary with the inverter ratio? 9 Save your design on floppy disc. Note: In order to use the Analysis---Parametric Analysis facility, a simulation of the circuit has to be made first using the Simulate----Start simulation menu and viewing the Voltage v. Time window.