CPME 424 Digital System Design
Laboratory Exercise No. 02
Handout 1
1. A 4-bit Ripple Carry Counter Illustrating Multiple Module
Instantiation in Verilog:
We can significantly reduce the complexity of our complete design by breaking it into
several modules and then interconnecting those modules in the top design file. A module
provides a template from which actual objects can be created. When a module is invokes
Verilog creates, a unique object from the template. The process of creating objects from a
module template is called instantiation, and the objects are called instances. In this lab we
will design a 4 bit ripple carry counter to elaborate multiple module instantiation. See
Handout 2 for verilog Code of the counter.
2. Stimulus for Testing Verilog Designs in Aldec 5.4 Environment:
Writing a good test bench (stimulus) is essential in checking the functionality of our
design. In this section we will see to write simple test benches to test our designs in Aldec
environment. Handout 2 has sample test-bench to test the 4
Step 1. The design file should already be present and compiled in your Aldec design.
Step 2. Add a new file but not though wizard as we did for design files.
Figure 2. A new file is being added through Empty files and Verilog Source files
option.
Step 3. Now write your test bench in verilog and once you have done compile it and add
all the signals that we have used to interact with the design to the waveform.
Following things could be helpful in writing a test bench:
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1. The name of the verilog test bench file could be any but we suggest file names in
the format <name of module under test>_tb.v.
2. The test bench do not contain any ports, unless, test bench is also accepting test
data from outside.
3. The signals that will use as input to the module under test should be declared as
reg and signals that will use as output to module under test should be declared as
wire.
4. The default time unit in aldec is ps. In order to create easily visible wave forms
either set time delays in nanosecond eg.: #100000 or zoom in the wave form.
5. Use $finish (see section 3 of this handout) to finish your test bench at a particular
time. Run until option in Aldec could also finish your test bench within an
indicated limit.
6. Statements within an initial block are sequential. Thus all #delays(see section 3)
used within an initial block are sequential.
7. Different initial blocks run parallel. Therefore #delays in different initials blocks
are parallel to each other. Care should be taken not to assign a signal two values at
the same time in different initial blocks.
A sample test bench for the full adder that we have designed in last lab session is shown
is figure 3.
Figure 3. A test bench is added to the design.
Now compile the test bench and set it as the Top Level Module and add all the signals
connected with the ports of module under test to the waveform and run simulation. We
will get a waveform as shown in fig. 4.
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Figure 4. Waveform of the test bench
Figure 5. $display messages are displayed in Console Window
3. Incorporating Delays in your Design:
The reg can be declared in the same way as wire. The general format is:
reg [n:0] variables;
We can model and simulate elements delay in verilog through statement #delay. In the
statements below:
#100 a = 1’b0;
b=1’b1;
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Values’0’ and ‘1’ will be assigned to ‘a’ and ‘b’ after 100 unit time. This delay is the
model of Combinational Logic Delay of element a. Please note that these statements are
sequential thus if we write like this:
#100 a = 1’b0;
#100 b=1’b1;
assign #100 c=1’b1;
Now ‘a’ has 100 unit time delay and ‘b’ has 200 unit time delay with respect to a
common starting point. We can also say that ‘b’ has a delay of 100 unit time after ‘a’ has
been assigned.
Delay could also added like this:
a = #100 1’b0;
b = #50 1’b1;
This delay is called Transport Delay and here it is different for ‘a’ and ‘b’. Therefore,
‘a’ will be assigned ‘0’ after 100 unit time and ‘b’ will be assigned 1 after 50 unit time.
We can use both delays together as:
#100 a = #10 c & d;
#100 b = # 30 c ^ d;
4. More Behavioral System Tasks:
1. $display:
Using the $display is the basic way to print out results and it could be used very similarly
to printf() statement in C. Some simple examples are shown below:
$display(“hello verilog”);
$display(“The value of a is %b, the value of b is %b”,a,b);
Symbol
%b
%d
%h
%o
%s
Table 1. Format Specifiers use in $display
Format
Binary
decimal
hexadecimal
Octal
String
2. $monitor:
If you want to print results as they change, use the $monitor system task. Unlike $display,
which only prints once, $monitor automatically prints out whenever any of the signal it is
printing changes., so we only need to call it once. Only one $monitor can be activated at a
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time. So if we want to change what is being printed just execute another $monitor system
task and the new $monitor becomes the active print-on-change task. We can stop
$monitor from printing by using the command $monitoroff and can also restart it by using
$monitoron.
3. $time:
This task can be use to display time and can be used with $monitor and $display to print
the time with signal value.
Simple statements using these three system tasks are:
$monitor("time is %d value of sum is %b",$time,sum);
$display("time: %d sum is wrong",$time);
4. $finish:
This task is used to end the simulation. Simulation should be ended after a time sufficient
to observe all signals i.e. it should end after all circuit delays have been expired other
wise simulations results will not be correct. We can add delay to $finish like this:
#10000 $finish;
LAB Assignments:
1. The 4 bit counter given in handout 2 currently counts uptill 15 before returning to
zero. Make appropriate changes in the test-bench so that it counts only uptill 5.
2. Repeat above exercise, but this make the counter to count 0-15 5 times. That is it
should count till 15 and then start again.
3. Write test benches in verilog to show output values for all possible combination
of input in the waveform for the 3:8 decoder done last time. Add appropriate gate
delays for the gates used in your design. For example set the delays for AND/OR
gates as 20ps. Similarly set the delays for the wires as 15 ps.
4. Write combinational logic in terms of logic gate symbols of the 4-bit comparator
done last time. Also write the complete test bench to test your design. As in
exercise 3 add appropriate delays for
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