95 學年度上學期期中考解答
一、
1
Ο
2
X
3
a
4
b
5
Ο
6
Ο
7
Ο
8
Ο
9
Ο
10
X
11
Ο
12
X
13
X
14
Ο
15
X
16
Ο
17
X
18
X
19
X
20
Ο
二、
1. The memory-reference instructions use the ALU for an address calculation,
the arithmetic-logical instructions for the operation execution, and branches for
comparison.
2.
詳細解釋請參考課本所附 CD 裡的 Appendix B p.29~p36
3. A clocking methodology defines when signals can be read and when they can
be written. It is important to specify the timing of reads and writes because, if a
signal is written at the same time it is read, the value of the read could
95 學年度上學期期中考解答
correspond to the old value, the newly written value, or even some mix of the
two! Needless to say, computer designs cannot tolerate such unpredictability. A
clocking methodology is designed to prevent this circumstance. An
edge-triggered clocking methodology means that any values stored in a
sequential logic element are updated only on a clock edge.
三、
1. Floating-point addition isn’t associative.
EX: suppose x  1.5 ten  10 38 , y  1.5 ten  10 38 , z  1.0
x  ( y  z )  1.5 t e n 10 38  (1.5 t e n 10 38  1.0)
 1.5 t e n 10 38  (1.5 t e n 10 38 )  1.0  0.0
( x  y )  z  (1.5 t e n 10 38  1.5 t e n 10 38 )  1.0
 (0.0t e )n 1.0  1.0
T h e r e f oxr e (, y  z )  ( x  y )  z
2.
1
 1012  250 pico seconds  0.25ns
9
4  10
1
 1 012  1 6 6.7 p i c os e c o n d s
6  1 09
3.
CPU clock cycles A  I  2.0
CPU clock cycles B  I  1.2
Now we can compute the CPU time for each computer :
CPU time A  CPU clock cycles A  Clock cycle time A
 I  2.0  250 ps  500  I ps
Likewise, for B :
CPU time B  I  1.2  500 ps  600  I ps
Clearly, computer A is faster. The amount faster is given by the ratio of the execution times :
CPU performanc e A Execution time B 600  I ps


 1.2
CPU performanc e B Execution time A 500  I ps
We can conclude that computer A is 1.2 times as fast as computer B for this program.
4.
Benchmarks：programs specifically chosen to measure performance.
95 學年度上學期期中考解答
SPEC benchmark：A set of standard CPU-intensive, integer and floating point
benchmarks based on real programs.
SPEC benchmark：The latest release of the SPEC CPU benchmarks, which
consists of 12 integer and 14 floating-point programs, as shown in figure 4.5.
5.
 Execution time affected by improvemen

Amount of improvemen t
Execution time after improvemen t  
  Execution time unaffected

t




四、
1. Biased notation：A notation that represents the most negative value by 00 …
000two and the most positive value by 11 … 111two with 0 typically having the
value 10 … 00 two , thereby biasing the number bias has a nonnegative
representation.
2. Single precision：A floating-point value represented in a single 32-bit word.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s exponent
1 bit
fraction
8 bits
23 bits
Double precision：A floating-point value represented in two 32-bit words.
3.
The number -0.875 ten is also
 7 / 8 two or  7 / 2 3 ten
It is also represente d by the binary fraction
 111two / 2 3 ten or -0.111two
In scientific notation, the value is
 0.111two  2 0
and in normalized scientific notation, it is
 1.11two  2 1
The general representa tion for a single precision number is
(1) S  (1  Fraction )  2 ( Exponent-127)
When we subtract t he bias 127 from the exponent of  1.11two  2 1 , the result is
(1)1  (1  .1100 0000 0000 0000 0000 000 two )  2 (126127)
The single precision binary representa tion of  0.875 ten is t h e n
95 學年度上學期期中考解答
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
1 bits
0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0000000000
8bits
23bits
The double precision representation is
12




(1)1 (1  .1100 0000 0000  0000 0000 0000)  2 (10221023)
4. The sign bit is 1, the exponent field contains 129, and the fraction field
contains 1*2^(-2) = 1/4, or 0.25. Using the basic equation,
(1) S  (1  Fraction )  2 ( Exeponent-Bias )  (1)1  (1  0.25)  2 (129127)
 1  1.25  2 2
 1.25  4
 5.0
.
五、
1. (1) Simplicity favors regularity. P.50
(2) Smaller is faster. P.53
(3) Make the common case fast. P.58
(4) Good design demands good compromises. P.63
2. (1) Register addressing, where the operand is a register
(2) Base or displacement addressing, where the operand is at the memory
location whose address is the sum of a register and a constant in the instruction
(3) Immediate addressing, where the operand is as constant within the
instruction itself
(4) PC-relative addressing, where the address is the sum of the PC and a
constant in the instruction
(6) Pseudodirect addressing, where the jump address is the 26 bits of the
instruction concatenated with the upper bits of the PC
95 學年度上學期期中考解答
1. Immediate addressing
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
+
Register
Byte
Halfword
Word
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
+
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
3. 因為 subtract immediate 可用加補數作到,無須再多一個 instruction.
4. Loop: sll
add
lw
bne
add
j
EXIT:
$t1, $s2, 2
$t1, $t1, $s2
$t0, $0($t1)
$t0, $s5, EXIT
$s3, $s3, 1
Loop