CSE 171 Lab 2. September 19-21, 2005.
EXPERIMENT: Xilinx ISE and Hardware Description Languages
References
1.
Text, pages 39-49, 87-91.
2.
171Lab2Fa05Tutorial.doc (available on class website)
3.
PLDT-3 Pinouts: PLDT3PinOuts.doc (available on class website)
4. ABEL – HDL Reference Manual
http://www.latticesemi.com/lit/docs/manuals/abel_ref.pdf
5. Verilog Reference Manual
http://eesun.free.fr/DOC/VERILOG/verilog_manual1.html#1.0
6. The Verilog Golden Reference Manual
http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf.
7. Verilog Hardware Description Language Reference Manual
http://www.et5.tu-harburg.de/Lehre/Praktikum/Cadence_digital/Verilog_Reference_Manual.pdf
LAB
1. Download the files 171Lab2Fa05Tutorial.doc, hex7seg.abl, SW7seg.abl, hex7seg.v,
SW7seg.v, and SW7seg.ucf from the class website and save on your USB drive. Print out a
copy of the file 171Lab2Fa05Tutorial.doc.
2. Implement an ABEL program on the PLDT-3 board by following the tutorial given in
171Lab2Fa05Tutorial.doc. Demonstrate the operation of the board to your lab instructor.
3. Implement the same logic function in Verilog by making a new project called Lab2v and
adding the files hex7seg.v, SW7seg.v, and SW7seg.ucf to this project. Follow similar steps as
in Part 2, but select XST(VHDL/Verilog) as the synthesis tool when you create the project.
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Demonstrate the operation of the board to your lab instructor.
Answer questions 5 – 8 on the class website for next week:
5. What are the basic steps required to implement a logic circuit on a CPLD using a hardware
description language such as ABEL or Verilog?
6. How are inputs, outputs, and nodes defined in ABEL and Verilog? How are specific pin
numbers assigned in each case? Give an example.
7. What behavioral statements in ABEL and Verilog can be used to map a set of input signals to
a set of output signals in a combinational logic circuit? Give examples.
8. How are individual modules “wired together” in the top-level design in ABEL and in
Verilog? Give an example of each.
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