Course Syllabus
ECE526L – Digital Design with Verilog and System Verilog Laboratory
Department of Electrical & Computer Engineering
1. Course Number and Name:
2. Credit Units/Contact Hours:
3. Course Coordinator:
ECE526 L– Digital Design with Verilog and
System Verilog Laboratory
1/3
Ronald W. Mehler
4. Text, References & Software
Recommended Text:
ECE 526L Verilog HDL Laboratory Manual
Software
Cadence NC Verilog simulator
5. Specific Course Information
a. Course Description
A series of exercises and experiments covering bottom-up structural design and top-down
behavioral design using Verilog and SystemVerilog (IEEE Std. 1800) for circuit description and
design verification. Lab exercises emphasize use of professional compilation and simulation
tools for design validation.
b. Prerequisite by Topic
ECE 320/L. Corequisite: ECE 526. Students need a thorough understanding of Boolean algebra,
combinational and sequential digital circuits and number systems (binary, hexadecimal).
c. Elective Course
6. Specific Goals for the Course
a. Specific Outcomes of Instructions – After completing this course the students should be able to:
1. The ability to code and simulate any digital function in Verilog HDL.
2. Know the difference between synthesizable and non-synthesizable code.
3. Understand library modeling, behavioral code and the differences between then.
4. Understand the differences between simulator algorithms.
5. Learn good coding techniques per current industrial practices.
6. Understand logic verification using Verilog simulation.
b. Relationship to Student Outcomes
This supports the achievement of the following student outcomes:
a. An ability to apply knowledge of mathematics, science, and engineering to the analysis of
electrical and computer engineering problems.
b. An ability to design and conduct scientific and engineering experiments, as well as to analyze
and interpret data.
c. An ability to design systems which include hardware and/or software components within
realistic constraints such as cost, manufacturability, safety and environmental concerns.
e. An ability to identify, formulate, and solve electrical and computer engineering problems.
g. An ability to communicate effectively through written reports and oral presentations.
k. An ability to use modern engineering techniques for analysis and design.
m. An ability to analyze and design complex devices and/or systems containing hardware and/or
software components.
7. Topics Covered/Course Outline
The following are detailed contents of the course:
Laboratory #1: Introduction to hardware Modeling and Simulation in Verilog
The student will get familiar with Cadence Verilog XL software and laboratory
equipment
Laboratory #2: Structural Modeling in Verilog
The student will model master-slave flip-flop using primitive gates
Laboratory #3: Design Hierarchy in Verilog
The student will model an 8-bit register with design hierarchy
Laboratory #4: 5-bit counter Behavioral Modeling
The student will model, simulate and test a 5-bit counter using behavioral constructs.
Laboratory #5: Modeling with Continuous Assignments
The student will model, simulate and test a scalable Multiplexer
Laboratory #6: Carry Select Adder Modeling
The student will model, simulate a Carry Select Adder and test its functionality.
Laboratory #7: Memory Modeling
The student will model, simulate and test memory a module.
Laboratory #8: Arithmetic Logic Unit Modeling
The student will design, model, simulate and test an arithmetic logic unit.
Laboratory #9: Modeling a Sequence Controller
The student will design, model, simulate and test a sequence controller.
Laboratory #10: Central Processing Unit Modeling
The student will design, model, simulate and test a CPU.
Prepared by:
Ronald W. Mehler, Professor of Electrical and Computer Engineering, October 2012
Ali Amini, Professor of Electrical and Computer Engineering, March 2013