ECE 111, Winter 2015
• Professor Bill Lin
– Office hours: TBD, 4310 Atkinson Hall
• Lectures:
– Section A00: MWF 10-10:50a, PETER 102
– Section B00: MWF 11-11:50a, PETER 102
• No Discussion Sections
• TAs:
Section A00: Steven Okai and Jainam Shah
Section B00: Jinwen Huang and Tianyi Yang
Office hours: TBD
Note: You may get help from any of the 4 TAs during their office hours.
• Goal: Learn Verilog-based chip design
• Project 1: Simple Fibonacci Calculator
– Due 1/23, Pass/No Pass
• Project 2: RLE Processor
– Due 2/11, Pass/No Pass
– Must re-do if not within 20% of average performance
– Interim report: TBD
• Final Project: SHA1 Security Processor
– Due 3/18 (Wed finals week), grading on performance
Altera Software
• See Software Downloads Page
which links to this:
• Quartus II Web Edition for Windows
– Quartus II Software
– ModelSim-Altera Edition
– Arria II device support
Icarus Verilog
• Another simulator
• Just runs together with your testbench and
prints out whatever is specified in the
More Information
• No textbook for this class. Verilog information
on class website. Also tutorial examples
• This is NOT a lecture-based class. Class time
used to talk about Verilog in the beginning,
but mostly about project information for the
rest of the quarter.
• Projects done in teams of 2 students.
Useful Altera Websites
• Verilog HDL Basics (50 minutes online course)
• Demonstration Center