University of Portland
School of Engineering
5000 N. Willamette Blvd.
Portland, OR 97203-5798
Phone 503 943 7314
Fax 503 943 7316
Functional Specifications
Project BAT: B^2 Logic to ABEL
Translator
Contributors:
Jamie Quint
Ian Tagge
Approvals
Name
Dr. Vegdahl
Date
Name
Date
Dr. Lillevik
Insert checkmark (√) next to name when approved.
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FUNCTIONAL SPECIFICATIONS
PROJECT BAT
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Revision History
Rev.
0.9
Date
09/20/06
UNIVERSITY OF PORTLAND
Author
I.Tagge
Reason for Changes
Initial draft
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Table of Contents
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Summary.......................................................................................................................
1
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Introduction ..................................................................................................................
2
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Background .................................................................................................................. 2
Requirements ............................................................................................................... 3
Overview ..................................................................................................................................................3
Compatibility and Interface .....................................................................................................................3
101 ...........................................................................................................................................................4
Abel 7.0 ....................................................................................................................................................4
102 ...........................................................................................................................................................4
B^2 Logic Release 3.1 with BLT/MOSIS Comptatible LS Library Parts ..............................................4
103 ...........................................................................................................................................................4
*nix Server Interface ................................................................................................................................4
151 ...........................................................................................................................................................4
GAL16V8 .................................................................................................................................................4
152 ...........................................................................................................................................................4
Write BAT such that future releases may support additional ICs .........................................................4
B^2 Logic Interpretation ..........................................................................................................................4
Command Line Interface ........................................................................................................................4
Conclusions ................................................................................................................. 6
Appendices................................................................................................................... 7
UNIVERSITY OF PORTLAND
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List of Figures.
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Figure 1. Block Diagram of.BAT Product ......................................................................................................3
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FUNCTIONAL SPECIFICATIONS
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Summary
1
Project BLT is B^2 Logic to ABEL converter. It will run from the Unix command line, take a
single file as input, and produce a single file as output. It will facilitate the design to
production function of integrated circuits (ICs) by allowing the conversion of a visual
schematic to ABEL hardware description language (HDL) code.
The intended user of this software is any user of the B^2 Logic design program who wants
to translate their design into HDL code, most likely electrical engineering students. The
user will benefit by saving the time normally required to complete this process by hand
and will not actually need any knowledge of HDL in order to design and fabricate a chip.
BAT will save a significant amount of time and reduce the possibility for human error
because the end user will no longer be required to translate a schematic into ABEL HDL
by hand. Team Bridgeport feels that this is the ideal time to take on such a project
because of the access to knowledgeable faculty to assist us with this project.
The initial release of the software will provide described functionality for strictly two-input
logic gates from the LS library, and will be programmable to a single type of target chip,
such as GAL16V8. The program is not meant to intelligently determine the ideal chip to
use for each individual design. It is also not meant to determine whether or not the B^2
Logic design can actually fit on the selected chip. These functions will not be included in
any future release.
The long-term purpose of this project is to allow B^2 Logic circuit schematics to be
completely translatable to ABEL for all chips that ABEL can program. This will allow the
end user to complete the entire design function in B^2 Logic and subsequently use the
translation application to generate the HDL code which can be opened in ABEL. The top
priority of this project is the desired feature set, which the team feels goes hand in hand
with quality.
Success for this project will be determined by taking a B^2 Logic file from a previous year’s
project, running it through our software, and fabricating a chip using the outputted ABEL
HDL code. This chip will then be built and tested against the previous design to confirm
correct
functionalit
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Introduction
2
This document, the functional specification, is written for the developers and advisors of
this project. The developers will use this document to communicate the goals and
implementation details of this project. The advisors will be able to use this document to
assess these goals.
This document is organized into three sections, the background, requirements, and
conclusions. The background is an introduction to the technical details of the software
involved in this project. The requirements explain the technical components of the project
and how they are achieved. The conclusion is an overview of this entire process.
Chapter
Background
3
B^2 Logic is a powerful tool for designing and testing schematics for digital logic circuits in
a visual environment. This software is not sufficient in and of itself because it is not
capable of producing output that can be programmed directly to an integrated circuit (IC).
ABEL is a hardware design language (HDL) whose code can be tested and outputted in a
format that can be programmed directly to an IC.
These two programs are
complementary in that B^2 provides visual design with testing, and ABEL interfaces
directly with the IC. Project BLT serves to combine the power of these two programs by
acting
as
a
converter
from
B^2
Logic
to
ABEL.
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Requirements
4
This chapter contains the body or “bulk” of the document. Start with an overview, and then
break your product into the top-level specifications. For each major section, create a table
of the requirements and then follow it with a written description.
Overview
The product solves the problem of extra work previously needed to implement a digital
logic circuit design from a visual schematic. In the past, this task required the engineer to
design and test the circuit in B^2 logic and then manually translate this to ABEL HDL code.
With this product the engineer can convert the EDF file output from B^2 Logic to fully
compatible ABEL code.
Figure 1. Block Diagram of BAT Product
Compatibility and Interface
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100. Software Compatibility
101
Abel 7.0
102
B^2 Logic Release 3.1 with BLT/MOSIS Comptatible LS Library Parts
103
*nix Server Interface
150. Chip Compatibility
151
GAL16V8
152
Write BAT such that future releases may support additional ICs
B^2 Logic Interpretation
201
Handle any configuration of logic parts supported by BLT/MOSIS library
Project BLT will be able to handle any configuration of the logic parts supported by the
BLT/MOSIS compatible library. The GAL16V8 has 8 dedicated inputs with 9 pins that can
be input, output or some other function. BAT will not take I/O pin-counts into account and
will assume that the user has designed the circuit with such constraints in mind.
Command Line Interface
301
Unix Command Line Interface
302
Syntax Error Handling
303
File-Based Error Handling
304
man Page
305
“-h” Switch
306
Output HDL file with same name, different extension
307
If file already exists, prompt user to cancel or overwrite
The user will access the BLT program through a Unix command line interface. The BLT
program will be activated by the command “bat chip inputfilepath” where inputfilepath is a
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complete file path to the desired input file and chip represents the type of chip to be
programmed. The program will handle errors in syntax and other file based errors such as
insufficient permissions or disk space by outputting an appropriate error message to the
command line. There will be a man page associated with this program as well as a “-h”
switch, which the user may reference to learn the appropriate program syntax. On
success, the program will output an HDL file with a different extension, but the same
name, as the input file. The program will exit quietly unless the output file already exists, in
which case it will prompt the user to overwrite (detailed in Appendix A).
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Conclusions
5
The BAT project will allow engineers to save significant amounts of time converting visual
schematics to HDL code.
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Appendices
See Attached PDFs.
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