University of Portland
School of Engineering
5000 N. Willamette Blvd.
Portland, OR 97203-5798
Phone 503 943 7314
Fax 503 943 7316
Functional Specifications
Project BAT: B2 Logic to ABEL
Translator
Contributors:
Jamie Quint
Ian Tagge
Approvals
Name
Dr. Vegdahl
Date
Name
Date
Dr. Lillevik
Insert checkmark (√) next to name when approved.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
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FUNCTIONAL SPECIFICATIONS
PROJECT BAT
REV. 1.0
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Revision History
Rev.
0.9
1.0
Date
09/20/06
10/06/06
UNIVERSITY OF PORTLAND
Author
I. Tagge
I. Tagge
Reason for Changes
Initial draft
Updated for 1.0 release
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Table of Contents
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Summary.......................................................................................................................
1
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Introduction ..................................................................................................................
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Background .................................................................................................................. 2
Requirements ............................................................................................................... 3
Overview ..................................................................................................................................................3
Block Diagram .........................................................................................................................................3
Compatability and Interface ...................................................................................................................3
Software Compatibility ............................................................................................................................3
Chip Compatibility ...................................................................................................................................3
B2 Logic Interpretation .............................................................................................................................3
Command Line Interface ........................................................................................................................3
Conclusions ................................................................................................................. 5
Appendices................................................................................................................... 6
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List of Figures.
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Figure 1. Block Diagram of.BAT Product ......................................................................................................3
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FUNCTIONAL SPECIFICATIONS
PROJECT BAT
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FUNCTIONAL SPECIFICATION
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Summary
1
Project BLT is a B2 Logic to ABEL converter. It will run from the Unix command line, take a
single file as input, and produce a single file as output. It will facilitate the design to
production function of integrated circuits (ICs) by allowing the conversion of a visual
schematic to ABEL hardware description language (HDL) code
The intended user of this software is any user of the B2 Logic design program who wants
to translate their design into HDL code, most likely electrical engineering students ,
however, professionals may find this product useful as well. The user will benefit by saving
the time normally required to complete this process by hand and will not actually need any
knowledge of HDL in order to design and fabricate a chip. Team Bridgeport feels that this
is the ideal time to take on such a project because of the access to knowledgeable faculty
to assist us with this project.
The prototype release of the software will provide described functionality for BLT/MOSIS
compatible LS parts and will be programmable to a single type of target chip, the
GAL16V8. The program is not meant to intelligently determine the ideal chip to use for
each individual design. It is also not meant to determine whether or not the B2 Logic
design can actually fit on the selected chip. These functions will not be included in any
future release.
The long-term purpose of this project is to allow B2 Logic circuit schematics to be
completely translatable to ABEL for all chips that ABEL can program. This will allow the
end user to complete the entire design function in B2 Logic and subsequently use the
translation application to generate the HDL code which can be opened in ABEL. The top
priority of this project is the desired feature set, which the team feels goes hand in hand
with quality.
Success for this project will be determined by taking a B2 Logic file from a number of
previous years’ projects, running them through our software, and programming chips
using the outputted ABEL HDL codes. These chips will be implemented in circuit and
tested against the previous designs to confirm correct functionality.
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Introduction
2
This document, the functional specification, is written for the developers and advisors of
this project. The developers will use this document to communicate the goals and
implementation details of this project. The advisors will be able to use this document to
assess these goals.
The functional specification is organized into three sections: background, requirements,
and conclusion. The background is an introduction to the technical details of the software
involved in this project. The requirements explain the technical components of the project
and how they are achieved. The conclusion is an overview of this entire process.
Chapter
Background
3
B2 Logic is a powerful tool for designing and testing schematics for digital logic circuits in a
visual environment. This software is not sufficient in and of itself because it is not capable
of producing output that can be programmed directly to an integrated circuit (IC). ABEL is
a hardware design language (HDL) whose code can be tested and output in a format that
can be converted directly to an IC. These two programs are complementary in that B2
provides visual design with testing, and ABEL interfaces directly with the IC. Project BLT
serves to combine the power of these two programs by acting as a converter from B2
Logic to ABEL.
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Requirements
4
Overview
The product solves the problem of extra work previously needed to implement a digital
logic circuit design from a visual schematic. Currently, this task requires an engineer to
design and testa circuit in B2 Logic, then manually translate it to ABEL HDL code. the BAT
progam the engineer will be able to convert a B2 Logic EDF file output to fully compatible
ABEL code.
Figure 1. Block Diagram of BAT Product
Compatibility and Interface
100. Software Compatibility
101
B2 Logic Release 3.1 with BLT/MOSIS Compatible LS Library Parts will be used to generate the
source EDF files.
102
The output will be a file containing ABEL 7.0 code.
103
BAT will use a *nix server interface.
150. Chip Compatibility
151
A GAL16V8 CPLD will be used as the initial target chip.
152
BAT will be written such that future releases may support additional ICs.
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B2 Logic Interpretation
201
BAT will handle any configuration of logic parts supported by BLT/MOSIS library
Project BLT will be able to handle any configuration of the logic parts supported by the
BLT/MOSIS compatible library. The GAL16V8 has 8 dedicated inputs with 9 pins that can
be input, output or some other function. BAT will not take I/O pin-counts into account and
will assume that the user has designed the circuit with such constraints in mind.
Command Line Interface
301
The user will interact with BAT through a Unix Command Line Interface
302
Syntax Error Handling will be implemented that will return user-friendly error messages
indicating the source (i.e. command line input, illegal part usage, etc.) and location (if
applicable) of the error.
303
File-Based Error Handling will be implemented to alert the user of file-related issues that may
include invalid file types, non-existent or corrupt files.
304
A ‘man Page’ will be available on the server (see Appendix)
305
Output HDL file will have the same name, but a different extension, as the input file.
306
If file already exists, the user will be prompted to cancel or overwrite.
The user will access the BAT program through a Unix command line interface. The BAT
program will be activated by the command “bat chip inputfilepath” where inputfilepath is a
complete file path to the desired input file and chip represents the type of chip to be
programmed. The program will handle errors in syntax and other file based errors such as
insufficient permissions or disk space by outputting an appropriate error message to the
command line. There will be a man page associated with this program (See Appendix B),
which the user may reference to learn the appropriate program syntax. On success, the
program will output an HDL file with a different extension, but the same name, as the input
file. The program will exit quietly unless the output file already exists, in which case it will
prompt the user to overwrite (See Appendix A).
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Conclusions
5
The BAT project will allow engineers to save significant amounts of time converting visual
schematics to HDL code. BAT is a powerful tool, but does not set out to do all of the
engineer’s work for him. As with any engineering tool, the engineer will have to abide by
certain limitations in order that that tool may be fully utilized. This software is designed to
work in conjunction with BLT, thus it will not be able to handle such things as hierarchies
or the entire LS library. Ideally, BAT will eventually be compatible with several ICs, but
even this functionality will be limited. The engineer will still have to determine the proper
IC to be used, and design the circuit with that chip and its capabilities in mind. When used
properly, BAT can be a powerful tool for converting schematics to HDL code, but it is
certainly not intended as a design tool, but a translator.
UNIVERSITY OF PORTLAND
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Appendices
See Attached PDFs.
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