University of Portland
School of Engineering
5000 N. Willamette Blvd.
Portland, OR 97203-5798
Phone 503 943 7314
Fax 503 943 7316
Functional Specifications
Project BAT: B2 Logic to ABEL
Translator
Contributors:
Jamie Quint
Ian Tagge
Approvals
Name
Dr. Vegdahl
Date
Name
Date
Dr. Lillevik
Insert checkmark (√) next to name when approved.
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Revision History
Rev.
0.9
0.95
1.0
Date
09/20/06
10/06/06
11/8/06
UNIVERSITY OF PORTLAND
Author
I. Tagge
I. Tagge
I. Tagge
Reason for Changes
Initial draft
Updated for 0.95 release
Updated for 1.0 release
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Table of Contents
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Summary.......................................................................................................................
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Introduction ..................................................................................................................
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Background .................................................................................................................. 3
Requirements ............................................................................................................... 4
Overview ..................................................................................................................................................4
Compatibility and Interface .....................................................................................................................4
B2 Logic Interpretation. ...........................................................................................................................6
Command Line Interface ........................................................................................................................6
Conclusions ................................................................................................................. 7
Appendices................................................................................................................... 8
Appendix A ..............................................................................................................................................8
Appendix B ........................................................................................................................................... 11
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List of Figures.
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Figure 1. Block Diagram of.BAT Product ......................................................................................................8
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Summary
Project BAT is a B2 Logic to ABEL converter. It will facilitate the design to production
function of integrated circuits (ICs) by allowing the conversion of a visual schematic to
ABEL hardware description language (HDL) code
The intended user of this software is any user of the B2 Logic design program who wants
to translate their design into HDL code, most likely electrical engineering students;
however, professionals may find this product useful as well. The user will benefit by saving
the time normally required to complete this process by hand. Team Bridgeport feels that
this is the ideal time to take on such a project because of the access to knowledgeable
faculty to assist us with this project.
The prototype release of the software will provide described functionality for BLT/MOSIS
compatible LS parts and will be programmable to a single type of target chip, the
GAL16V8. The program is not meant to intelligently determine the ideal chip to use for
each individual design. It is also not meant to determine whether or not the B2 Logic
design can actually fit on the selected chip. These functions will not be included in any
future release.
The long-term purpose of this project is to allow B2 Logic circuit schematics to be
completely translatable to ABEL for all chips that ABEL can program. This will allow the
end user to complete the entire design function in B2 Logic and subsequently use the
translation application to generate the HDL code which can be opened in ABEL. The top
priority of this project is the desired feature set, which the team feels goes hand in hand
with quality.
Success for this project will be determined by taking a B2 Logic file from a number of this
years’ projects, running them through our software, and programming chips using the
outputted ABEL HDL codes. These chips will be implemented in circuit and tested against
to confirm correct functionality. We will additionally be performing testing with fabricated
test circuits, assuring that all parts of the BLT/MOSIS Library will be sufficiently tested.
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Introduction
This document, the functional specification, is written for the developers and advisors of
this project. The developers will use this document to communicate the goals and
implementation details of this project. The advisors will be able to use this document to
assess these goals.
The functional specification is organized into three sections: background, requirements,
and conclusion. The background is an introduction to the technical details of the software
involved in this project. The requirements explain the technical components of the project
and how they are achieved. The conclusion is an overview of this entire process.
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Background
B2 Logic is a powerful tool for designing and testing schematics for digital logic circuits in a
visual environment. This software is not sufficient in and of itself because it is not capable
of producing output that can be programmed directly to an integrated circuit (IC). ABEL is
a hardware design language (HDL) whose code can be tested and output in a format that
can be converted directly to an IC. These two programs are complementary in that B2
provides visual design with testing, and ABEL interfaces directly with the IC. Project BLT
serves to combine the power of these two programs by acting as a converter from B2
Logic to ABEL.
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Requirements
Chapter 4 details the essential functions and compatibilities of BAT.
Overview
The product solves the problem of extra work previously needed to implement a digital
logic circuit design from a visual schematic. Currently, this task requires an engineer to
design and test a circuit in B2 Logic, and then manually translate it to ABEL HDL code.
With the BAT progam the engineer will be able to convert a B2 Logic EDF file output to
fully compatible ABEL code. Figure 1 is a high level diagram of BAT’s functionality as
described above.
Figure 1. Block Diagram of BAT Product
The following tables list the requirements of BAT in no particular order.
Compatibility and Interface
100. Software Compatibility
Number
Description
101
B2 Logic Release 3.1 with BLT/MOSIS Compatible LS Library Parts (as of date – if change will not
support) will be used to generate the source EDF files (see Appendix A).
102
The output will be a file containing ABEL 7.0 code.
103
BAT will use a *nix server interface.
The following is a list of the parts BAT will support. (This list is synonymous with
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the BLT//MOSIS library
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• Input Pad
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• Input Pad Clock .
• Output Pad
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• 1-to-2 Bus Connector
• 1-to-3 Bus Connector
• 1-to-4 Bus Connector
• 1-to-8 Bus Connector
• 2-to-1 Bus Connector
• 3-to-1 Bus Connector
• 4-to-1 Bus Connector
• 8-to-1 Bus Connector
• Net Connector
• High Voltage - VDD
• Ground - GND
• Buffer - BUF1
• Inverter - INV
• Exclusive OR - XOR2
• 2 Input OR - NOR2C
• 2 Input NOR - NOR2
• 2 Input NAND - NAND2
• 2 Input AND - NAND2C
• 3 Input NOR - NOR3
• 3 Input NAND - NAND3
• 3 Input AND - NAND3C
• 4 Input NAND - NAND4
• 4 Input AND - NAND4C
• D Flip Flop - DFFPC
• Tri-State Buffer - BUFZ
• Multiplexer 1-of-2 - MUX2
150. Chip Compatibility
Number
Desctription
151
A 44-pin Xilinx CPLD will be used as the initial target chip.
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B Logic Interpretation
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Number Description .
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201
BAT will handle any configuration of logic parts supported by BLT/MOSIS library (as of
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Project BLT will be able to handle any configuration of the logic parts supported by the
BLT/MOSIS compatible library. The Xilinx CPLD 44 pins which will be more than sufficient
to accommodate any MOSIS chip design (34 pins max). BAT will not take I/O pin-counts
into account and will assume that the user has designed the circuit with such constraints in
mind.
Command Line Interface
Number
Description
301
The user will interact with BAT through a *nix Command Line Interface
302
Syntax Error Handling will be implemented that will return user-friendly error messages
indicating the source (i.e. command line input, illegal part usage, etc.) and location (if
applicable) of the error.
303
File-Based Error Handling will be implemented to alert the user of file-related issues that
may include invalid file types, non-existent or corrupt files.
304
A ‘man Page’ will be available on the server (see Appendix B) (GET PDF’s into Word)
305
Output HDL file will have the same name with a .abl extention, as the input file.
306
If file already exists, the user will be prompted to cancel or overwrite.
The user will access the BAT program through a Unix command line interface. The BAT
program will be activated by the command “bat chip inputfilepath” where inputfilepath is a
complete file path to the desired input file and chip represents the type of chip to be
programmed. The program will handle errors in syntax and other file based errors such as
insufficient permissions or disk space by outputting an appropriate error message to the
command line. There will be a man page associated with this program (See Appendix B),
which the user may reference to learn the appropriate program syntax. On success, the
program will output an HDL file with a different extension, but the same name, as the input
file. The program will exit quietly unless the output file already exists, in which case it will
prompt the user to overwrite (See Appendix B).
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Conclusions
The BAT project will allow engineers to save significant amounts of time converting visual
schematics to HDL code. BAT is a powerful tool, but does not set out to do all of the
engineer’s work for him. As with any engineering tool, the engineer will have to abide by
certain limitations in order that that tool may be fully utilized. This software is designed to
work in conjunction with BLT, thus it will not be able to handle such things as hierarchies
or the entire LS library. Ideally, BAT will eventually be compatible with several ICs, but
even this functionality will be limited. The engineer will still have to determine the proper
IC to be used, and design the circuit with that chip and its capabilities in mind. When used
properly, BAT can be a powerful tool for converting schematics to HDL code, but it is
certainly not intended as a design tool, but a translator.
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Appendices
The following section contains the appendices referenced in the document.
Appendix A – B2 Logic/ABEL Context Free Grammars
B2 Logic EDF File Backus-Naur Form Description
<EDF> ::= <setup> <input/output-definition> <contents> <design-root>
<input/output-definition> ::=
"(cell toplevel (cellType generic))"
"(view view_1 (viewType netlist))"
"(interface"
{<port-info>}
")"
<contents> ::=
"(contents"
{<instances>}
{<netlist>}
")"
<instances> ::=
"(instance" <instance-name>
"(viewRef viewnamedefault"
"(cellRef" <cell-name>")"
"))"
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<netlist> ::=
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"(net" <net-name>
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"(joined"
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{<connection>}+
"))"
<port-info> ::= "(port" <port-name> "(direction" <direction>"))"
<port-name> ::= ("IN"<digit>+ | "OUT"<digit>+) | "P"<digit>+
<direction> ::= "input" | "output"
<instance-name> ::= "INST"<digit>+
<connection> ::= "(portref <port-name> {"(instanceref <instance-name>)"}"
<digit> ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
Note: Setup information and design-root are both parts of the EDF file that will be ignored
by our program (they are extraneous) therefore they have been omitted from this
description.
ABEL Backus-Naur Form Description
<abelcode>::= <headerline1> <headerline2> <headerline3> <inputdefs>+ <outputdefs>+
[<sets>+] <logic> <end>
<headerline1> ::= "MODULE" <module_name> <EOL>
<headerline2> ::= "TITLE" "'" <project title> "'" <EOL>
<headerline3> ::= "U1 device " "'" <partname> "';" <EOL>
<inputdefs> ::= <inputname> "pin" <pinnumber> ["istype" <type>] ";" <EOL>
<outputdefs> ::= <outputname> "pin" <pinnumber> ["istype" <type>] ";" <EOL>
<type> ::= "attr" | "com" | "reg" | "neg" | "pos" | "buffer" | "dc" | "invert" | "reg_D"
| "reg_T" | "reg_SR" | "reg_JK" | "reg_G" | "retain" | "xor"
<pinnumber> ::= “1” | “2” | “3” | “4” | “5” | “6” | “7” | “8” | “9” | “11” | “12” | “13” | “14” | “15”
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| “16” | “17” | “18” | “19”
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<sets> ::= <setname> "=[" <varstart> ".." <varend> "];"
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<varstart> ::=.<inputname> | <outputname>
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<varend> ::= <inputname> | <outputname>
<logic> ::= "equations" <EOL> {<equations>}
<equations> ::= <boolean> | <truth_table> | <combo>
<boolean> ::= <var> "=" ([<operator>] <var> <operator> <var>)* <EOL>
<combo> ::= "WHEN" <condition> "THEN" <var> "=" <var> "ELSE" <var> "=" <var>
<condition> ::= <var> | (<var> "=" <var> | <num>)
<num> ::= <digit>+
<digit> ::= "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9"
<var> ::= (<inputname> | <outputname> | <setname> | <constants>) [<dotext>]
<dotext> ::= "." ("J" | "K" | "R" | "S" | "T" | "Q" | "PR" | "RE" |"ACLR" | "ASET" | "CLR"
| "SET" | "AR" | "AP" | "SR" | "SP" | "LE" | "LH" | "CE" | "OE" | "FC" | "COM")
<constants> ::= "." ("C" | "K" | "U" | "D" | "F" | "P" | "SVn" | "X" | "Z") "."
<operator> ::= "!" | "&" | "#" | "$" | "!$" | "-" | "+" | "*" | "/" | "%" | "<<"
| "<<" | "==" | "!=" | "<" | "<=" | ">" | ">=" | "=" | "?=" | ":+=" | "?:="
<*name> ::= <string>
<string> ::= (<digit> | <letter>) (<digit> | "_" | <letter>)+
<letter> ::= "a" | "b" | "c" | "d" | "e" | "f" | "g" | "h" | "i" | "j" | "k" | "l" | "m" | "n" | "o" | "p" | "q"
| "r" | "s" | "t" | "u" | "v" | "w" | "x" | "y" | "z" | "A" | "B" | "C" | "D" | "E" | "F" | "G"
| "H" | "I" | "J" | "K" | "L" | "M" | "N" | "O" | "Q" | "R" | "S" | "T" | "U" | "V" | "W"
| "X" | "Y" | "Z"
<end> ::= "END" <module_name>
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Appendix B – Use Case
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Use Case: File Conversion
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Primary Actor: Electrical Engineer.
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Goals: To convert an EDF file to ABEL HDL code.
Preconditions: Engineer has completed design of a digital logic circuit in B^2 Logic and desires
to implement this design on an integrated circuit. Engineer has terminal window open on a
system which has the BLT program installed and is at a blank command prompt.
Trigger: The engineer decides to convert EDF file exported from B^2 Logic to ABEL HDL code.
Scenario:
1. Engineer: activates the BAT program by typing in the command "bat chip inputfilepath" where
inputfilepath is a complete file path to the desired input file or a file in the current working
directory. Chip represents the type of chip to be programmed.
2. Engineer: observes success message indicating the inputted file has been successfully
converted and outputted.
Exceptions:
1. No chip/input/output name given (program returns error message indicating correct
program syntax): engineer repeats scenario with proper inputs.
2. Invalid chip name given (program returns a list of compatible chip names): engineer repeats
scenario with a valid chip name.
3. Output file name already exists (program prompts user to overwrite): engineer
chooses to overwrite file, or renames existing file and repeats scenario.
4. Not enough disk space to output file (program returns error message indicating lack of disk
space): engineer deletes files to make space and then repeats scenario.
5. No permissions to write given output file or read given input file (program returns error
message indicating lack of permissions): engineer acquires appropriate permissions or selects
input and output files for which he or she has proper permissions and repeats scenario.
6. No inputs given (program returns error message indicating correct program syntax): engineer
repeats scenario with proper inputs.
7. Unreadable or corrupted input file (program returns error message indicating input file is
unreadable): engineer repeats scenario with compatible file.
8. Input file does not exist (program returns error message indicating input file cannot be found):
engineer repeats scenario with an existing file.
9. Too many arguments given (program returns error message indicating too many arguments
were given and that the program does not support multiple file conversions at one time): engineer
repeats scenario with proper number of file arguments.
Priority: Essential
When Available: First Version
Frequency of Use: Irregularly Frequent (may not be used for months at a time, but may be used
many times in a small time period)
Channel to actor: Via terminal command prompt
Secondary Actors: None
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Open Issues: None
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