Chapter 1
Introduction to CMOS Circuit
Design
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
Outline




Introduction
MOS Transistor Switches
CMOS Logic
Circuit and System Representation
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2
Binary Counter
a
Present
state
Next state
a
b
A
B
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
A = a’b + ab’
B = a’b’ + ab’
A
b
B
CK
CLR
Source: Prof. V. D. Agrawal
Advanced Reliable Systems (ARES) Lab.
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1-bit Multiplier
A
C
B
C=AxB
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Switch: MOSFET
 MOSFETs are basic electronic devices used
to direct and control logic signals in IC design
 MOSFET: Metal-Oxide-Semiconductor FieldEffect Transistor
 N-type MOS (NMOS) and P-type MOS (PMOS)
 Voltage-controlled switches
 A MOSFET has four terminals: gate, source,
drain, and substrate (body)
 Complementary MOS (CMOS)
 Using two types of MOSFETs to create logic
networks
 NMOS & PMOS
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P-N Junctions
 A junction between p-type and n-type
semiconductor forms a diode.
 Current flows only in one direction
p-type
n-type
anode
cathode
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6
NMOS Transistor
 Four terminals: gate, source, drain, body
 Gate–oxide–body stack looks like a capacitor




Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal–oxide–semiconductor (MOS) capacitor
Even though gate is no longer made of metal
Source
Gate
Drain
Polysilicon
SiO2
n+
n+
p
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bulk Si
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NMOS Operations
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
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D
bulk Si
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8
NMOS Operations (Cont.)
 When the gate is at a high voltage:




Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
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D
bulk Si
Jin-Fu Li, EE, NCU
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PMOS Operations
 Similar, but doping and voltages reversed




Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
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bulk Si
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Threshold Voltage
 Every MOS transistor has a characterizing
parameter called the threshold voltage VT
 The specific value of VT is established during
the manufacturing process
 Threshold voltage of an NMOS and a PMOS
NMOS
PMOS
VA
Drain
VDD
Gate
Mn
VA +
VGSn Source
VA=1
Mn On
VTn
0
Gate-source voltage
VGSp
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VA Gate
VA=0
Mn Off
Logic translation
VA
Source
+ VDD
Mp
VDD
VDD-|VTp|
Drain
Gate-source voltage
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0
VA=1
Mp Off
VA=0
Mp On
Logic translation
11
MOS Transistor is Like a Tap…
Source: Prof. Banerjee, ECE, UCSB
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MOSFET & FinFET
G
S(D)
MOSFET
D(S)
Si-Substrate
D(S)
D(S)
G
G
S(D)
Oxide
Si-Substrate
Bulk FinFET
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S(D)
Buried Oxide
Si-Substrate
SOI FinFET
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13
IG & SG FinFETs
 According to the gate structure, FinFET can
be classified as
 Independent-Gate (IG) FinFET
 Short-Gate (SG) FinFET
D(S)
G
S(D)
D(S)
G
G
S(D)
Oxide
Si-Substrate
IG FinFET
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Oxide
Si-Substrate
SG FinFET
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MOS Switches
 NMOS symbol and characteristics
Vth
5v
5v
0v
5v-Vth
0v
 PMOS symbol and characteristics
0v
Vth
5v
5v
Vth
0v
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CMOS Switch
 A complementary CMOS switch
 Transmission gate
-s
Symbols
a
C
b
s
a
-s
b
a
b
s
s
0v
5v
Characteristics
5v
0v
0v
5v
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CMOS Logic-Inverter
 The NOT or INVERT function is often
considered the simplest Boolean operation
 F(x)=NOT(x)=x’
Vin
Vout
Vdd
0
Vdd
Vin
Vout
Vdd
1
1
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Vdd
0
Vdd/2
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Indeterminate
logic level
17
Combinational Logic
 Serial structure
a
S1=0
S2=0
S1=0
S2=1
S1=1
S2=0
S1=1
S2=1
S1
0
S1
1
0 a!=b
a!=b
1 a!=b
a=b
S2
S2
b
a
S1=0
S2=0
S1=0
S2=1
S1=1
S2=0
S1=1
S2=1
S1
S1
0
1
0
a=b
a!=b
1
a!=b
a!=b
S2
S2
b
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Combinational Logic
 Parallel structure
S1=0
S2=0
a
S1=0
S2=1
S1=1
S2=0
S1=1
S2=1
S1
0
S1
S2
1
0 a!=b
a=b
1
a=b
S2
a=b
b
S1=0
S2=0
a
S1=0
S2=1
S1=1
S2=0
S2
S1
S1=1
S2=1
S1
0
1
0
a=b
a=b
1
a=b
a!=b
S2
b
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NAND Gate
Output
A
0
1
0
1
1
1
1
0
A
B
B
A
B
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Output
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NOR Gate
A
A
B
0
1
0
1
0
1
0
0
Output
B
A
B
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Output
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Compound Gate
 F  (( AB )  (CD ))
A
C
B
A
B
D
F
A
C
B
D
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C
D
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F
22
Structured Logic Design
 CMOS logic gates are intrinsically inverting
 The output always produces a NOT operation
acting on the input variables
 For example, the inverter shown below
illustrates this property
1
a=1
VDD
f=0
0
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23
Structured Logic Design
 The inverting nature of CMOS logic circuits
allows us to construct logic circuits for AOI
and OAI expressions using a structured
approach
 AOI logic function
 Implements the operations in the order AND then
OR then NOT
 E.g., g ( a , b , c , d )  a .b  c .d
 OAI logic function
 Implements the operations in the order OR then
AND then NOT
 E.g., g ( a , b , c , d )  ( a  b )  ( c  d )
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24
Structured Logic Design
 Behaviors of nMOS and pMOS groups
 Parallel-connected nMOS
 OR-NOT operations
 Parallel-connected pMOS
 AND-NOT operations
 Series-connected nMOS
 AND-NOT operations
 Series-connected pMOS
 OR-NOT operations
 Consequently, wired groups of nMOS and
pMOS are logical duals of another
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Dual Property
 If an NMOS group yields a function of the form
g  a  (b  c )
then an identically wired PMOS array gives the
dual function
G  a  (b  c )
where the AND and OR operations have been
interchanged
 This is an interesting property of NMOS-PMOS
logic that can be exploited in some CMOS designs
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An Example of Structured Design
 X  a  b  (c  d )
VDD
c
b
d
a
Group 2
Group 1
X
b
Group 3
a
c
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d
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An Example of XOR Gate
 Boolean equation of the two input XOR gate
 a  b  a  b  a  b, this is not in AOI form
 But, a  b  a  b  a  b, this is in AOI form
 Therefore, a  b  ( a  b )  a  b  a  b
VDD
a
b

a

b
a
VDD
a


b




b
ab
a
a
b
b
XOR Gate
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b
a
ab
a
b
XNOR Gate
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Multiplexer
A
B
1
0
Y
Y
S1 S0
S
-S
A
A
Y
S
11
10
01
00
A
B
C
D
B
Y
C
B
-S
D
S1
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-S1
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S0
-S0
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Static CMOS Summary
 In static circuits at every point in time (except
when switching), the output is connected to
either Vdd or Gnd through a low resistance path
 Fan-in of n (or n inputs) requires 2n (n N-type and n Ptype) devices
 Non-ratioed logic: gates operate independent of
PMOS or NMOS sizes
 No path ever exists between Vdd and Gnd: low
static power
 Fully-restored logic (NMOS passes “0” only and
PMOS passes “1” only
 Gates must be inverting
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Design Flow for a VLSI Chip
Specification
Function
Behavioral Design
Function
Structural Design
Function
Timing
Power
Physical Design
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Circuit and System Representations
 Behavioral representation
 Functional, high level
 For documentation, simulation, verification
 Structural representation





System level – CPU, RAM, I/O
Functional level – ALU, Multiplier, Adder
Gate level – AND, OR, XOR
Circuit level – Transistors, R, L, C
For design & simulation
 Physical representation
 For fabrication
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Behavior Representation
 A one-bit full adder (Verilog)
module fadder(sum,cout,a,b,ci);
output sum, cout;
input a, b, ci;
reg sum, cout;
ci
always @(a or b or ci) begin
sum = a^b^ci;
cout = (a&b)|(b&ci)|(ci&a);
end
endmodule
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b
a
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fadder
cout
sum
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Structure Representation
 A four-bit full adder (Verilog)
b
a
module adder4(s,c4,a,b,ci);
output[3:0] sum;
output c4;
a[0]
b[0] a[1]
b[1] a[2]
b[2] a[3]
b[3]
input[3:0] a, b;
co[1]
co[2]
co[0]
input ci;
ci
a0
a1
a2
a3
reg[3:0] s;
s[0]
s[1]
s3]
s[2]
reg c4;
wire[2:0] co;
s
adder4
fadder a0(s[0],co[0],a[0],b[0],ci);
fadder a1(s[1],co[1],a[1],b[1],co[0]);
fadder a2(s[2],co[2],a[2],b[2],co[1]);
fadder a3(s[3],c4,a[3],b[3],co[2]);
endmodule
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Physical Representation
 Layout of a 4-bit NAND gate
Vdd
Vdd
in1
in2
in3
in1
Out
in4
Out
in2
in3
in4
Gnd
in1 in2
in3 in4
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35