Ryerson University
Department of Electrical and Computer Engineering
COE328 – Digital Systems
Lab 1
Introduction to CAD Tools
10 marks (2 Week)
Due Date: Week 4
Objective:
Quartus II is used in the synthesis of digital logic design with Complex Programmable Logic
Devices (CPLDs) or Field Programmable Gate Arrays (FPGAs). You will learn how to prepare,
compile and simulate a logic design with Quartus II using three different methods: schematic
capture, truth table, and VHDL code.
Part B – Quartus II “Tutorial Introduction”
B.1 Installing Quartus II on Your Home Computer (Optional)
• System Requirements
o IBM PC using Windows 2000, XP or NT (3.51 or 4.0)
o CD drive for software installation
o Available memory > 48 MB
o Available Hard disk space > 80 MB
• Installation
o Insert the Quartus II CD that comes with the textbook and follow the on-screen instructions.
Alternatively, you can download Quartus II Web Edition from www.altera.com.
o A license file is required to run Quartus II. Go to www.altera.com to get your license
file. After you have provided Altera the required information, the license file will be emailed
to you along with instructions how to enable the software.
B.2 Pre-lab preparation
1. Print out the Quartus II Tutorial 1 (available from the course Web page or the Quartus II CD
that comes with the textbook).
2. You can do the prelab work on any SUN workstation on the department’s network, or on your
own home computer if you have installed Quartus II.
3. To save your files, create the subdirectory coe328. Under the directory coe328 create another
directory called lab1. This will be working directory for the design created in this tutorial.
4. Start up Quartus II at the command prompt on the SUN workstation, or click on the Quartus II
icon on your home computer. This will open the Quartus II window, which gives you access to
an integrated suite of several application tools.
B.3 Creating a Schematic Design
Schematic designs are created with the Block Editor tool of Quartus II.
• To start the Block Editor, start Quartus II, select ``File’’ then ``New’’; a new window will pop up,
select ``Block Diagram/Schematic File’’.
• Refer to Section B.2 of Quartus II Tutorial 1 and enter the schematic represented in Figure
B.4.
• Save the schematic by following the instructions in Quartus II Tutorial 1.
B.4 Compiling and Simulating a Design
A design is verified by compiling, creating input waveforms (test vectors), simulating and
viewing the results.
• To open the compiler select ``Tools’’ then ``Compiler Tool’’.
• Click on the ``Start’’ button to compile the design. A message window will pop up at the end of
the compilation displaying the number of warnings and errors. If your design is error-free, then
proceed to the next step; otherwise, correct the design and re-compile it.
• Before a design can be simulated, it is necessary to create the input signals (called test vectors)
to the circuit. The Quartus II Waveform Editor can be used for this purpose. Follow the
instructions in Section B.2.4 of Quartus II Tutorial 1 to create the test vectors for the simulation.
• Simulate the circuit by selecting ``Tool’’ then ``Simulator Tool’’. A simulation window will pop
up. Select ``Functional Simulation’’, specify the filename of the test vectors created in the last
step, click ``Generate Functional Simulation Netlist’’, and finally ``Start’’. After the simulation,
click ``Report’’ then ``Simulation Waveforms’’ to check the simulation results. Print out the
waveforms by moving the mouse pointer on ``Simulation Waveforms’’, pressing the right mouse
button and select ``Print’’. Show the result to your instructor.
B.5 Design Entry Using Truth Tables
In this section we will design a logic circuit using truth table. We will implement the truth table
shown in Figure B.25 of Section B.4 (see Quartus II Tutorial 1). It will be entered into the CAD
system by drawing a timing diagram, which is equivalent to truth table.
• Open the Waveform Editor
• Specify the type of the file to be created by selecting File then Save As. In the box labeled File
Name, type the name timing1.vwf.
• Specify the input and output signals (rQuartus II Tutorial 1)
• Specify a waveform for the output of the circuit that corresponds to its truth table
• Select File then Save. Show the simulation result to your instructor.
B.6 Mixed Design-Entry Methods
Here we will create a schematic that includes the circuit designed using the truth table in the
previous section. Use the same directory as for the previous projects see Section B.5 of the
Quartus II Tutorial 1).
• Open the Graphic Editor
• Specify the type of the file to be created by selecting File then Save As. In the box labeled File
Name, type the name mixed1.bdf.
• Import the timing1 circuit into the Graphic Editor.
• Follow the procedure of Section B.5 of Quartus II Tutorial 1 and draw the schematic of Figure
B.30. Save the schematic.
• Show the simulation result to your instructor.