“Where ICs are in the IEEE”



10,000 members
70+ chapters located worldwide
Foster information exchange in electronics
◦
◦
◦
◦

Distinguished Lectures
Online tutorials
International and regional conferences
Journals & magazines
Part of IEEE with 400,000 members
Publications &
Conferences
Journal of Solid-State Circuits (JSSC)
 #1 technical source for circuits
 Most downloaded IEEE journal articles
 Top cited reference in US Patent applications
Solid-Sate Circuits Magazine
 Discusses historical milestones, trends and
future developments
 Articles by leaders from industry and
academia in a tutorial and editorial style
International and Regional Conferences
 4 International Sponsored Conferences
 Technically co-sponsored conferences
Chapter & DL Events
Annual SSCS DL Tour
Swedish SOC Conference (May 2011)
Individual DL
Presentations
SSCS-Italy: International
Analog VLSI Workshop
(September 2011)
Knowledge ...
staying current with the fast changing world of solid-state
circuit technology
Community …
local and global activities, unparalleled networking
opportunities, chapter activities, electing IEEE SSCS
leadership
Profession …
empowering members to build and own their careers,
mentoring, making the world a better place
Recognition …
Best Paper Awards, IEEE Fellow & Field Awards,
Student Travel Grants & Pre-doctoral Achievement Award
…
Organize chapter events
 Participate in & organize conferences
 As an author
 As a reviewer
 Compete in a student design contest
 Nominate senior members & fellows

Energy Limits in A/D Converters
August 29, 2012
Boris Murmann
murmann@stanford.edu
A/D Converter ca. 1954
P/fs = 500W/50kS/s = 10mJ
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html
8
ADC Landscape in 2004
-6
10
-8
P/f snyq [J]
10
-10
10
-12
10
ISSCC & VLSI 1997-2004
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
9
ADC Landscape in 2012
-6
10
-8
P/f snyq [J]
10
-10
10
-12
10
ISSCC & VLSI 1997-2004
ISSCC & VLSI 2005-2012
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html
10
Observation
• ADCs have become substantially
“greener” over the years
• Questions
– How much more improvement can we
hope for?
– What are the trends and limits for
today’s popular architectures?
– Can we benefit from further process
technology scaling?
11
Outline
• Fundamental limit
• General trend analysis
• Architecture-specific analysis
– Flash
– Pipeline
– SAR
– Delta-Sigma
• Summary
12
Fundamental Limit
Brickwall
LPF at fsnyq/2
1
C
2
Class-B
2
1  VFS 
2  2  fs
SNR 
kT
fsnyq
C
OSR
Pmin  CVFS fs  VDD
Emin
Pmin

 8kT  SNR
fsnyq
VDD  VFS
[Hosticka, Proc. IEEE 1985; Vittoz, ISCAS 1990]
13
ADC Landscape in 2004
-6
10
-8
Energy [J]
10
-10
10
-12
4x/6dB
-14
ISSCC & VLSI 1997-2004
Emin
10
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
14
ADC Landscape in 2012
-6
10
-8
Energy [J]
10
-10
10
-12
4x/6dB
-14
ISSCC & VLSI 1997-2004
ISSCC & VLSI 2005-2012
Emin
10
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
15
Normalized Plot
8
10
ISSCC & VLSI 1997-2004
ISSCC & VLSI 2005-2012
6
EADC/Emin
10
4
10
2
10
~10,000
100x in 8 years
~100
3-4x in 8 years
0
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
16
Aside: Figure of Merit Considerations
• There are (at least) two widely used ADC
figures of merit (FOM) used in literature
• Walden FOM
– Energy increases 2x per bit (ENOB)
– Empirical
Power
FOM  ENOB
2
 fsnyq
• Schreier FOM
– Energy increases 4x per bit (DR)
– Thermal
 BW 
FOM  DR(dB)  10log 

– Ignores distortion
P


17
FOM Lines
-6
10
-8
Energy [J]
10
-10
10
-12
ISSCC & VLSI 1997-2004
ISSCC & VLSI 2005-2012
Emin
-14
Walden FOM = 10fJ/conv-step
Schreier FOM = 170dB
10
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
• Best to use thermal FOM for designs above 60dB
18
Walden FOM vs. Speed
1.E+05
FOMW [fJ/conv-step]
1.E+04
1.E+03
1.E+02
1.E+01
ISSCC 2012
VLSI 2012
ISSCC 1997-2011
VLSI 1997-2011
1.E+00
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
fsnyq [Hz]
• FOM “corner” around 100…300MHz
19
Schreier FOM vs. Speed
180
ISSCC 2012
VLSI 2012
170
ISSCC 1997-2011
VLSI 1997-2011
FOMS [dB]
160
150
140
130
120
110
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
fsnyq [Hz]
20
Energy by Architecture
-6
10
-8
P/f s [J]
10
-10
10
Flash
Pipeline
SAR

-12
Other
FOM=100fJ/conv-step
FOM=10fJ/conv-step
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
21
Flash ADC
2B-1
Dout
Vin
Ecomp
Eenc
2B-1 Decision Levels
• High Speed
– Limited by single comparator plus encoding logic
• High complexity, high input capacitance
– Typically use for resolutions up to 6 bits
22
Encoder
• Assume a Wallace encoder (“ones counter”)
• Uses ~2B–B full adders, equivalent to ~ 5∙(2B–B) gates


Eenc  5  2B  B  Egate
23
Matching-Limited Comparator

Cc
Cc
C
A 2VT

 A 2VT c
WL
Cox
A 2VTCox
Cc  2
 Cc min
VOS
3VOS
Simple Dynamic Latch
Assuming Ccmin = 5fF
for wires, clocking, etc.
Ecomp
2
VOS
1 Vinpp

4 2B
SNR[dB]  3
B
6
Offset
Required
capacitance
Confidence
interval
3dB penalty
accounts for
“DNL noise”
2


VDD
2B
2
2
  144  2  Cox A VT  2  Cc min VDD   2B  1


Vinpp


Matching

Energy

24
Typical Process Parameters
Process
[nm]
AVT
[mV-mm]
Cox
[fF/mm2]
AVT2Cox /kT
Egate [fJ]
250
8
9
139
80
130
4
14
54
10
65
3
17
37
3
32
1.5
43
23
1.5
25
Comparison to State-of-the-Art
-6
10
-8
10
Flash ISSCC & VLSI 1997-2012
Eflash65nm
Ecomp65nm
-10
Emin
[6]
P/f snyq [J]
10
[2]
[1]
-12
10
[5]
[3]
[4]
-14
10
-16
10
15
20
25
30
35
40
SNDR [dB]
[1] Van der Plas, ISSCC 2006
[2] El-Chammas, VLSI 2010
[3] Verbruggen, VLSI 2008
[4] Daly, ISSCC 2008
[5] Chen, VLSI 2008
[6] Geelen, ISSCC 2001 (!)
26
Impact of Scaling
-6
10
Flash ISSCC & VLSI 1997-2012
Eflash250nm
-8
P/f snyq [J]
10
Eflash130nm
Eflash65nm
Eflash32nm
-10
10
Emin
-12
10
-14
10
15
20
25
30
35
40
SNDR [dB]
27
Impact of Calibration (1)
-6
10
-8
10
Flash ISSCC & VLSI 1997-2012
Ecomp65nm
Ecomp65nm,cal
-10
Emin
P/f snyq [J]
10
-12
10
-14
10
-16
10
15
20
25
• Important to realize
that only comparator
power reduces
30
35
40
SNDR [dB]
3VOS
1 Vinpp

4 2BBcal
Bcal  3
28
Impact of Calibration (2)
-6
10
-8
10
Flash ISSCC & VLSI 1997-2012
Flash65nm
Flash65nm,cal
-10
Emin
P/f snyq [J]
10
-12
10
-14
10
-16
10
15
20
25
30
35
40
SNDR [dB]
29
Ways to Approach Emin (1)
• Offset calibrate each comparator
– Using trim-DACs
[El-Chammas, VLSI 2010]
8
Voutn
CAL
Vlo Vhi
Vrefn
8
Voutp

Dcalp
8
4
2
1
Decoder

Vinp
Vinn

Vrefp
CAL
Dcaln
Vlo Vhi
30
Ways to Approach Emin (2)
• Find ways to reduce clock power
• Example: resonant clocking
(54% below CV2)
[Ma, ESSCIRC 2011]
31
Raison D'Être for Architectures Other
than Flash…
-6
10
-8
P/f s [J]
10
-10
10
Flash
Pipeline
SAR

-12
Other
Eflash65nm
10
Eflash32nm
Emin
-14
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
32
Pipeline ADC
Align & Combine Bits
Dout
Vin
SHA
Stage 1
Vin1
Stage n-1

G11
G
-
ADC
DAC
D1
Vres1
Stage n
• Conversion occurs along
a cascade of stages
• Each stage performs a
coarse quantization and
computes its error (Vres)
• Stages operate
concurrently
– Throughput is set by the
speed of one single stage
33
Pipelining – A Very Old Idea
34
Typical Stage Implementation
[Abo, 1999]
Power
goes here
35
Simplified Model for Energy Calculation
C
C/2
C/4
C/2m
2
2
2
2
MSB
LSB
• Considering the most basic case
– Stage gain = 2  1 bit resolution per stage
– Capacitances scaled down by a factor of two
from stage to stage (first order optimum)
– No front-end track-and-hold
– Neglect comparator energy
36
Simplified Gain Stage Model
Feedback factor
Assumptions
C
2
1


C 3
C
2
1
C
Closed-loop gain = 2
gm
Infinite transistor fT (Cgs=0)
C/2
Ceff
C/2
Bias device has same
noise as amplifier device
gm
2
Ceff
1'
C
C 5
 1      C
2
2 6
Effective load capacitance
Thermal noise factor = 1,
no flicker noise
Linear settling only (no
slewing)
Nout  2
1 kT
kT
kT
6
5
 Ceff
Ceff
C
Total integrated output noise
37
Total Pipeline Noise
Nin,tot



kT 
1
kT  1
1
1

1   5
 2  1  1  ...

C  2
C 2

42
82
2
4


First sampler
3 kT
kT  1 1 1


5



...


2 C
C  4 8 16

kT
4
C
38
Key Constraints
1  Vinpp 


2 2 
SNR 
kT
4
C

2
Ceff
T /2
Ts / 2
 s

gm
 1  ln SNR
ln  
 d 

P  VDD
gm
 gm 


I
 D 
Thermal noise
sets C

Settling time
sets gm
gm sets power
39
Pulling It All Together
Settling
“Number of ”
Epipe  640  kT  SNDR  ln
Excess noise
Non-unity feedback
factor

VDD
penalty
2
 VDD 
1
1
SNDR  


 V  V
gm
DD
 inpp 
ID
Supply

utilization Transconductor
efficiency
• For SNDR = {60..80}dB, VDD=1V, gm/ID=1/(1.5kT/q),
Vinpp=2/3V, the entire expression becomes
Epipe  388...517  kT  SNDR
• For realistic numbers at low resolution, we must
introduce a bound for minimum component sizes
40
Energy Bound
• Assume that in each stage Ceff > Ceffmin = 50fF
• For n stages, detailed analysis shows that this
leads to a minimum energy of
Epipe,min  2n  Ceff min VDD
ln

SNDR

g 
 m 
 ID 
• Adding this overhead to Epipe gives the energy
curve shown on the next slide
41
Comparison to State-of-the-Art
-8
10
[4]
P/f snyq [J]
-10
10
[6]
[5]
[3]
[2]
[1]
-12
10
Pipeline ISSCC & VLSI 1997-2012
Epipe
-14
10
Emin
40
45
50
55
60
[1] Verbruggen, ISSCC 2012
[2] Chu, VLSI 2010
[3] Lee, VLSI 2010
65
70
SNDR [dB]
75
80
85
90
[4] Anthony, VLSI 2008
[5] Lee, ISSCC 2012
[6] Hershberg, ISSCC 2012
42
Ways to Approach Emin (1)
[Chu, VLSI 2010]
• Comparator-based SC circuits replace op-amps
with comparators
• Current ramp outputs
– Essentially “class-B” (all charge goes to load)
43
Ways to Approach Emin (2)
[Lee, VLSI 2010]
Similar:
[Lee, ISSCC 2012]
• Use only one residue amplifier
• Build sub-ADCs using energy efficient SAR ADCs
• Essential idea: minimize overhead as much as
possible
44
Ways to Approach Emin (3)
[Hershberg, ISSCC 2012]
• Completely new idea: ring amplifier
– As in “ring oscillator”
45
Ways to Approach Emin (4)
[Hershberg, ISSCC 2012]
• Class-C-like oscillations until charge transfer is
complete
– Very energy efficient
46
Expected Impact of Technology Scaling
• Low resolution (SNDR ~ 40-60dB)
– Continue to benefit from scaling
– Expect energy reductions due to reduced
Cmin and reduction of CV2-type contributors
• High resolution (SNDR ~ 70dB+)
– It appears that future improvements will
have to come from architectural innovation
– Technology scaling will not help much and
is in fact often perceived as a negative
factor in noise limited designs (due to
reduced VDD)
• Let’s have a closer look at this…
47
A Closer Look at the Impact of
Technology Scaling
• As we have shown
2
1
E
VDD
 VDD 
1


 V   g 
m
 inpp 
 
 ID 
• Low VDD hurts, indeed, but one should realize that
this is not the only factor
• Designers have worked hard to maintain (if not
improve) Vinpp/VDD in low-voltage designs
• How about gm/ID?
48
gm/ID Considerations (1)
30
180nm
90nm
gm/ID [S/A]
25
20
15
10
5
0
-0.2
-0.1
0
0.1
0.2
0.3
VGS-Vt [V]
0.4
0.5
0.6
• Largest value occurs in subthreshold ~(1.5kT/q)-1
• Range of gm/ID does not scale (much) with technology
49
gm/ID Considerations (2)
120
fT [GHz]
100
180nm
90nm
80
60
40
20
0
-0.2
-0.1
0
0.1
0.2
0.3
VGS-Vt [V]
0.4
0.5
0.6
• fT is small in subthreshold region
• Must look at gm/ID for given fT requirement to compare
technologies
50
gm/ID Considerations (3)
30
180nm
90nm
45nm
gm/ID [S/A]
25
20
15
10
5
0
20
40
60
fT [GHz]
80
100
• Example
– fT = 30GHz
– 90nm: gm/ID = 18S/A
– 180nm: gm/ID = 9S/A
• For a given fT, 90nm
device takes less current
to produce same gm
– Helps mitigate, if not
eliminate penalty due
to lower VDD (!)
51
ADC Energy for 90nm and Below
-6
10
-8
P/f snyq [J]
10
-10
10
-12
10
ISSCC & VLSI 1997-2012
90nm and below
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
52
Successive Approximation Register ADC
VDAC / VREF
VIN
VREF
DAC
1
3/4
5/8
1/2
1/2
3/4
5/8
11/16
21/32
41/64
VIN
Control
Logic
Clock
• Input is approximated via a binary search
• Relatively low complexity
• Moderate speed, since at least B+1 clock cycles
are needed for one conversion
• Precision is determined by DAC and comparator
Time
Classical Implementation
Ecomp
Edac
B
Elogic
B
Elogic  8
[McCreary, JSSC 12/1975]
gates 2fJ

B
bit gate
(somewhat optimistic)
54
DAC Energy
• Is a strong function of the switching scheme
• Excluding adiabatic approaches, the “merged capacitor
switching” scheme achieves minimum possible energy
[Hariprasath, Electronics Lett., 4/2010]
n1


2
Edac   2n32i 2i  1 CVref
i1
For 10 bits:
2
Edac  85CVref
55
DAC Unit Capacitor Size (C)
• Is either set by noise, matching, or minimum
realizable capacitance (assume Cmin = 0.5fF)
• We will exclude matching limitations here, since
these can be addressed through calibration
• Assuming that one third of the total noise power
is allocated for the DAC, we have
SNR 
1  Vinpp 


2 2 
2
kT
 Ncomp  Nquant
2B C
C  24kT  SNR 
1
 Cmin
B
2
2  Vinpp
56
Comparator
kT
Nin 
Cc
Cc
Cc
Simple Dynamic Latch
(Assuming Ccmin = 5fF)
Ecomp
Cc  24kT  SNR 
B
Thermal Noise
1
 Cc min
2
Vinpp
SNR[dB]  3
6
2

 1
VDD
2
  24kT  SNR  2  Cc min VDD    B

 2
Vinpp


Switching
probability
57
Comparison to State-of-the-Art
[7]
-8
10
[6]
P/f snyq [J]
-10
10
[5]
[3]
-12
[2]
[1]
10
[4]
SAR ISSCC & VLSI 1997-2012
ESARcomp
-14
ESAR
10
Emin
20
30
40
50
60
SNDR [dB]
[1] Shikata, VLSI 2011
[2] Van Elzakker, ISSCC 2008
[3] Harpe, ISSCC 2012
[4] Liu, VLSI 2010
70
80
90
[5] Liu, ISSCC 2010
[6] Hurrell, ISSCC 2010
[7] Hesener, ISSCC 2007
58
Ways to Approach Emin (1)
High Noise
Comp
Low Noise
Comp
[Giannini, ISSCC 2008]
Dynamic Noise
adjustment for
comparator power
savings
59
Ways to Approach Emin (2)
• Minimize unit caps as much as possible
for moderate resolution designs
– Scaling helps!
0.5fF unit capacitors
[Shikata, VLSI 2011]
60
Delta-Sigma ADCs
• Discrete time
– Energy is dominated by the first-stage
switched-capacitor integrator
– Energy analysis is similar to that of a
pipeline stage
• Continuous time
– Energy is dominated by the noise and
distortion requirements of the first-stage
continuous time integrator
– Noise sets resistance level, distortion sets
amplifier current level
– Interestingly, this leads to about the same
energy limits as in a discrete-time design
61
Overall Picture
-6
10
-8
P/f s [J]
10
Flash
Pipeline
SAR
-10
10

Other
Eflash32nm,cal
Epipe
-12
10
Esar
ECT
Emin
-14
10
20
30
40
50
60
70
SNDR [dB]
80
90
100
110
62
Summary
• No matter how you look at it, today’s ADCs are extremely
well optimized
• The main trend is that the “thermal knee” shifts very rapidly
toward lower resolutions
– Thanks to process scaling and creative design
• At high resolution, we seem to be stuck at E/Emin~100
– The factor 100 is due to architectural complexity and
inefficiency: excess noise, signal < supply, non-noise limited
circuitry, class-A biasing, …
• This will be very hard to change
– Scaling won’t help (much)
– Some of the recent data points already use class-B-like
amplification
– Can we somehow recycle the signal charge?
• Are there completely new ways to approach A/D
conversion?
63
http://www.wired.com/wiredenterprise/2012/08/upside/
64