In God We Trust
ECE Department, University of Tehran
Class presentation for the course: “Custom Implementation of DSP systems”
Presented by: Mohammad Haji Seyed Javadi
Instructor: Prof. S.M. Fakhraei
May 2013
This presentation is mainly based on :
M. Mehendale, et. al., “A true multistandard, programmable, low-power, full HD
video-codec engine for smart phone SoC”, ISSCC, page 226-228. IEEE, 2012
All the materials are copyrights of their respective authors as listed in references
Outline
 Video-codec concepts
 H.264 codec data flow
 Related implementations of video codec.
 IVA-HD architecture
 IVA-HD configurability
 OMAP4 architecture
 IVA-HD physical properties
 Comparison with previous works
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Video-Codec[1,2]
 CODE + DECODE ==> CODEC
 Application samples
 Camcorder
 Video conferencing
 Smart phone
 Various Standards
 MPEG-1, MPEG-2, H.263, H.264
 Concerning implementation issues
 Higher quality
 Lower power consumption
 Area efficiency
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As a sample: H.264/AVC
H.264 video-codec block diagram [1]
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Related works
 Low power video-codecs[4-6]
 Using single codec optimized circuitry
 Massive parallelism
 Lower voltage and frequency
 Drawbacks:



Targeted to a specific standard
Address either encode or decode
Not area efficient to support multiple video standards
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Related works (Cont’d)
 Multicore programmable processor[7]
 Support multiple standards
 Eight media processing engine (MPEs)
 Each MPE consists of RISC processor and co-processor
 Drawbacks:


Not scalable to meet full HD performance
Inefficient in terms of area and power
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Related works (Cont’d)
 Application processor[8]
 Decoupling stream processing and pixel processing
 Using 2 macro block pipelining
 Low power consumption (342 mW)
 Drawbacks:


Introduce a frame delay  higher latency
Can not support fixed bitrate encoding
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IVA-HD: Multi-standard video coding engine[3]
 Asynchronous
 Configurable pipeline
 Distributed control
 6 hardware accelerators
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IVA-HD architecture [3]
IVA-HD Configurability[3]
IVA-HD programmability/configurability to support various use cases[3]
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OMAP-4 Application Processor
OMAP44x block diagram[9]
OMAP-4 functional diagram[3]
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IVA-HD Physical Properties[3]
 45-nm CMOS process
 Clock frequency for H.264
 266 MHz (1080 P, 30 FPS)
 Power management techniques
 DVFS, AVS and ABB
 Supply Voltage
 1.1 V + AVS adjusted
 H.264 HP decode power
OMAP-4 chip micrograph[3]
 Range from 65 to 95 mW
 H.264 HP encode power
 Range from 100 to 145 mW
 Occupies less than 10% of OMAP4 chip area
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Comparison table[3]
Comparison with previous works [3]
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References
[1] Iain E. G. Richardson, “H.264 and MPEG-4 Video compression”, Wiley press 2003.
[2] T. Wiegand, et. al., “Overview of the H.264/AVC Video Coding Standard”, IEEE TCSVT, Vol.13,
No. 7, pp. 560-576, 2003.
[3] M. Mehendale, et. al., “A true multistandard, programmable, low-power, full HD video-codec
engine for smart phone SoC”, IEEE ISSCC, pp. 226-228, 2012.
[4] D. Finchelstein, et al., “A Low-Power 0.7-V H.264 720p Video Decoder”, ISSCC, pp. 173-176,
April, 2008.
[5] Y. Lin, et al., “A 242mW 10mm2 1080P H.264/AVC High-Profile EncoderChip”, ISSCC Dig. Tech.
Papers, pp. 314-315, Feb. 2008.
[6] Y. Kikuchi, “A 222mW H.264 Full-HD Decoding Application Processor with x512b Stacked
DRAM in 40nm”, ISSCC Dig. Tech Papers, pp. 326-327, Feb.2010.
[7] S. Nomura, et al., “A 9.7mW AAC-Decoding, 620mW H.264 720p 60fpsDecoding, 8-Core Media
Processor with Embedded Forward-Body-Biasing andPower-Gating Circuit in 65nm CMOS
Technology”, ISSCC Dig. Tech Papers, pp.262-263, Feb. 2008.
[8] K. Iwata, et al., “A 342mW Mobile Application Processor with Full-HD Multi-Standard Video
Codec”, ISSCC Dig. Tech. Papers, pp. 158-159, Feb. 2009.
[9] http://www.ti.com/product/omap4430
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