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Approach to design a compact reversible low power binary
comparator
Md Hasan Babu, H.
Computers & Digital Techniques, IET (Volume:8 , Issue: 3 )
DOI: 10.1049/iet-cdt.2013.0066
Publication Year: May 2014 Page(s):129-139
Project Title
: Approach to design a compact reversible low power binary
comparator
Domain
: VLSI
Reference
: IEEE
Publish Year
: May 2014 Page(s):129-139
D.O.I
: 10.1049/iet-cdt.2013.0066
Software Tool
: XILINX
Language
: Verilog HDL
Developed By
: Wine Yard Technologies, Hyderabad
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WYV68
Approach to design a compact reversible low
power binary comparator
Abstract:
Reversible logic has captured significant attention in recent time as reducing power
consumption is the main concern of digital logic design. It consumes less power by
recovering bit loss from its unique input–output mapping. In this study, the authors propose
a reversible low power n-bit binary comparator. An algorithm is presented for constructing a
compact reversible n-bit binary comparator circuit. The authors also propose two new
reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to
optimise the comparator. In addition, several theorems on the numbers of gates, garbage
outputs, quantum cost, ancilla input, power, delay and area of the reversible n-bit
comparator have been presented. The simulation results of the proposed comparator show
that the circuit works correctly and gives significantly better performance than the existing
ones. The comparative study shows that, as an example, for a 64-bit comparator, the
proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in
terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and
3.43% in terms of power over the existing best one. Area and power analysis also show that
the proposed design is the most compact as well as a low power circuit.
Existing method:
The binary comparator like of 1 bit,2 bit ….n bit ,comparators are designed by using
conventional gates like and, not, xor etc. using the Boolean expressions.
Proposed method:
The development in the field of nanometer technology leads to minimize the power
consumption of logic circuits. Reversible logic design has been one of the promising
technologies gaining greater interest due to less dissipation of heat and low power
consumption. In the digital design, the comparator is a widely used process. So, the
reversible logic gates and reversible circuits for realizing comparators like 1 bit,2 bit and
up to n bit binary reversible comparators using reversible logic gates is proposed.
The
proposed design leads to the reduction of power consumption compared with conventional
logic circuits.
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Applications:
1. Digital systems designing
2. Digital signal processing
3. Quantum computing
4. DNA computing,
5. Optical computing
Advantages:
1. Area Efficient circuits.
2. Low power Circuits
3. High speed circuits
Conclusion:
This paper has presented the design methodologies of a compact low power reversible n-bit
binary comparator. We have proposed an algorithm to design the compact reversible n-bit
comparator. In addition, we have proposed two reversible gates, namely, BJS and HLN
gates. We have proved the efficiency of the proposed design with several theorems and
lemmas. The required ancilla inputs, for the proposed circuit,is independent of n (for, n ≥ 2).
It has also been shown by comparative analysis that the proposed circuit has been
constructed with the optimum ‘number of gates’ (proposed circuit has 3n compared with 7n
−4 [18], 19], 9n [20] and 4n −2 [21]), ‘garbage outputs’ (proposed circuit has 4n − 3
compared with 5n −4 [18, 19], 6n – 6 [20], 5n −4 [21] and 5n −1 [23]), ‘quantum cost’
(proposed circuit has 13n − 5 compared with 16n – 10 [18, 19], 18n −9 [20], 14n [21] and
17n − 12 [23]), ‘power’ (proposed circuit requires 117.76n − 32.94 compared with 182.53n +
76.55 [18, 19], 268.23n − 239.2 [20] and 122.36n − 60.36 [21]) and ‘area’ (proposed circuit
needs 42.5n − 14.5 compared with 57.5n − 35 [18, 19], 90n − 77.5 [20] and 57.5n − 35 [21]).
Even though the timing delay of the proposed circuit (0.15n − 0.03 compared with 0.2n −
0.16 [18, 19], 0.23 * log2(n) + 0.1 [20] and 0.09 * log2(n) + 0.2 [21]) is not as less as the treebased designs, considering the optimization of all the parameters, the circuit outperforms
the existing ones in terms of scalability and efficiency. Simulations of the proposed circuit
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have shown that it works correctly. Since comparison of two numbers are useful in many
applications, the comparator circuits can be used in many operations inside the
microprocessor, communication systems, encryption devices, sorting networks, low power
circuits etc. [17, 19, 24].
Circuit Diagrams:
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Screen shots:
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