Unconditionally Stable Loop Design of Voltage-Mode Controlled
Synchronous Buck Converter, Part 1
By: Peyman Asadi, Amir Rahimi, and Parviz Parto, International Rectifier Co.
Design of voltage-mode controlled synchronous-buck converter can result to a conditionally
stable loop using conventional compensation-design methods. In such cases, the compensator
provides the desired loop bandwidth with good stability margin at nominal operating point while
load transient response indicates a robust performance of the converter.
However, the control loop becomes unstable at certain conditions such as the drop of input
voltage. To avoid these undesired situations, the compensation network is usually modified to
achieve unconditional stability.
The demand for wide input-voltage, high-frequency non-isolated synchronous buck converters has
rapidly increased in recent years. It is desired to design wide control loop bandwidth for this
converter to benefit the high frequency operation and minimize the number of output capacitors.
However, it is possible a wide loop-bandwidth design to be conditionally stable. Even though the
problem of conditionally stable converters is not new among power electronics engineers, it can
be ignored during application development and evaluation since common stability metrics such as
phase margin and load transient response at nominal condition do not reveal it.
This article reviews the problem of conditionally stable loop design of single phase voltage-mode
controlled non-isolated synchronous buck converter with examples and provides some design
guidelines to achieve unconditional stability.
I. Introduction
Constant frequency and low-noise operation of voltage-mode-controlled PWM scheme makes it
the popular candidate for high-performance non-isolated buck converter. In this scheme a
compensator network is required to achieve robust stability, good load and line regulation, and
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fast response to dynamic load variation. The compensator is usually implemented with an
Error/Amplifier and a network of Resistors and Capacitors (Figure 1) [Reference 1].
Fig. 1.
Buck converter with voltage-mode controlled PWM Scheme using error
amplifier.
Depending on the relative location of the zero of output capacitors (Fz0), switching frequency (Fs),
and desired closed loop bandwidth (Fo) different types of compensation networks are commonly
used as summarized in Table 1.
Table 1 - The compensation type and location of zero crossover frequency.
Compensator Type
Type II: (PI)
Type III-A: (PID)
Type III-B: (PID)
Relative location of Fo, Fz0, and Fs
Fz0  Fo  FS / 2
Fo  Fz0  FS / 2
Fo  FS / 2  Fz0
Output Capacitor Type
Electrolytic
POS-Cap
Ceramic
Details of compensation network design are explained in many references such as AN-1162 from
International Rectifier [1]. The implementation of Type II and Type III A/B compensator circuits
using voltage mode are shown in Figure 2. In brief, both compensators behave as an integrator in
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low frequencies to assure zero steady-state error. The output filter of the converter is usually an
LC filter, which creates a 180 degree phase lag in addition to 90 phase lag of the integrator.
Thus, to achieve good phase margin, one or two zeros (i.e., one for Type II and two for Type IIIA/B) are placed below and close to the zero crossover frequency of the gain (i.e., Fo). The zero(s)
of the compensator plus the zero of output capacitor(s) usually provide enough boost to the phase
of loop to keep it above -180 degree at every frequency below Fo. However, in some applications
the location of compensator zero(s) and/or output capacitor(s) zero are far from the resonance
frequency of output LC filter (FLC).
Consequently, the phase of loop drops to below -180 for a range of frequencies less than Fo and
then reaches again above -180 at Fo. In this case, if the loop gain drops to 0 db at zero crossover
frequency of the phase, the loop becomes unstable. Thus, the converter is called conditionally
stable. In general, a loop design that guarantees unconditional stability is preferred. A
straightforward way to avoid conditional loop design is either dropping Fo or placing the
compensator zero(s) around FLC.
P
Vout
2
Rf1
Rc1
--
Vout
Cc2
Rf1
Cf3
Cc1
Rf3
Z1
--
Z1
Ve
--
P1=0 Integration by Cc1
Integrator
Gain= 1/
(Rf1.Cc1)
Magnitude (db)
Vp
Magnitude (db)
Cc1
--
-Vp
Z2
Rf2
P1=0 Integration by
Cc1 1/
Integrator Gain=
(Rf1.Cc1)
Cc2
Rc1
P3
Ve
--
Rf2
P2
FZ1
FP2
(a) Type II Compensator
Fig. 2.
FZ1 FZ2
Log(f)
FP2 FP3 Log(f)
(b) Type III A/B compensator
Type II and TYPE III-A/B compensators with asymptotic gain
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Two situations that can result to conditionally stable loop are demonstrated as examples in Figure
3 and Figure 4. More details on the performance of a conditionally stable converter and design
80
120
70
105
60
90
50
75
40
60
30
45
Increase of Fz0
20
30
10
15
0
Phase (Degree)
Gain (db)
guidelines to achieve unconditional stability are given with an example in succeeding sections.
0
Negative Phase Range
-10
-15
-20
1
Frequency (kHz)
Magnitude Fz0=10kHz
Phase Fz0=10kHz
Magnitude Fz0=20kHz
Phase Fz0=20kHz
Magnitude Fz0=30kHz
Phase Fz0=30kHz
60
160
45
120
30
80
15
40
Increase of Fo
0
0
Phase (Degree)
Frequency response of a converter with Type II compensator, where
the Fz0 varies from 10 kHz to 30 kHz.
Gain (db)
Fig. 3.
-30
100
10
Negative Phase Range
-15
-40
-30
1
10
Magnitude Fo=120kHz
Phase Fo=120kHz
Fig. 4.
Frequency (kHz)
100
Magnitude Fo=150kHz
Phase Fo=150kHz
-80
1,000
Magnitude Fo=180kHz
Phase Fo=180kHz
Frequency response of a converter with Type III-B compensator, where the
target bandwidth is changing from 120 kHz to 180 kHz.
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Figure 3 shows the frequency response of a converter with Type II compensator, where Fo is
designed for 75 kHz and FLC equals to 3 kHz*. The zero of the output capacitors (Fz0) is located at
about 10 kHz. The compensator has a zero at 0.75 times of FLC, the first pole at 0 Hz, and the
second pole at 300 kHz (i.e., Fs/2). The location of Fz0 varies due to manufacturing tolerances,
aging, ambient temperature, and addition of bypass ceramic capacitors on the output of converter.
Assuming for this example, Fz0 changes from 10 kHz to 30 kHz, the bandwidth drops from
75 kHz to 34 kHz and the phase margin decreases from 80 to above 45. Although the loop
is stable with more than 45 phase margin at Fz0 equal to 30 kHz, the phase drops below zero
about 4 kHz to 5 kHz frequency range. Thus, the loop becomes conditionally stable.
Application engineer can either drop the loop bandwidth or select a Type III-A compensator
such that unconditional stability would be achieved.
In another example with ceramic output capacitors and 1 MHz switching frequency, a Type III-B
is used and the compensator is changed to achieve bandwidth of 120 kHz to 180 kHz (Figure 4).
Even though all of the designs guarantee a phase margin of over 55, the minimum phase gets
negative for the 180 kHz design.
*
In this picture and following ones, the phase of loop includes the 180 degree inversion by negative feedback. Thus,
phase of above zero is desired for unconditional stability.
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