17 February, 2016
SERLINK
VME MODULE
F.FORMENTI, M.MOREL
a
EP DIVISION / ED GROUP
ABSTRACT
The function of the SERLINK module is to test transmission of
20 bit data through a serial link using 30 meters of shielded
twisted pair cable (AWG 36) at 155Mb/s.
1
1. TRANSMITTER
a) tx_fifo
b) Altera_tx
c) Transmitter
2. RECEIVER
a) Receiver
b) Altera_rx1
c) Altera_rx2
d) rx_fifo
3. VME
4. CONCLUSION
1. TRANSMITTER
2
a) tx_fifo
The tx_fifo section is composed of 4 IDT 7205-20 8k x 9
CMOS parallel fifos manufacture by IDT.
They are connected between one the 32 bit VME dataway and
the 20 bit tx_fifo_databus.
The tx_fifo circuit diagram is shown on page 30.
b) Altera_tx
This Altera PLD performs the following functions:
- 25 bit shift register comprising of 20 bits of data, 1 start
bit and 4 odd parity bits formatted as follows:
DATA
OUT
STA
BIT
0
X
X
X
X
X
OP
X
X
X
X
X
OP
X
X
X
X
X
OP
X
X
X
X
X
OP
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RX
FIFO
DATA
RX
FIFO
PAR
DOWN
CNT
3
7
8
9
10
11
12
13
2
14
15
16
17
18
19
1
20
21
22
23
24
25
0
26
27
28
29
- A down counter to divide the 155Mhz clock by 25.
- The logic necessary to provide a Tx_fifo_read_clock* signal.
All the logic is integrated into an ALTERA EPM 7064SLC44-5
PLD and is shown on pages 17 to 20.
c) Transmitter
3
30
31
The heart of the transmission section is centered around a
S3015 OC-3 ATM interface circuit manufacture by AMCC.
ATM is an Asynchronous Transfer Mode system.
When serial data is present at input of the transmitter, the
S3015 VCO synchronizes directly to the incoming data, which
is then retimed to enable CMI encoding (Coded Mark Inversion
format). The CMI encoder accepts serial data at 155.52Mb/s.
After encoding the data into CMI format, the result is shifted
out with transitions at twice the basic data rate. A 19.44Mhz
TTL oscillator is connected to the reference input and
synthesized up to the 155Mhz output frequency.
The S3015 provides PECL (Positive Emitter Coupled Logic)
outputs, which are directly connected to a CLC006 serial cable
driver from National Semiconductor.
A PLL MC88915 provides the 155Mhz clock from the 19.44Mhz
reference (The 155Mhz from the S3015 in not available in CMI
mode.)
The circuit diagram of the transmitter section is shown on
page 31.
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2. RECEIVER
a) Receiver
The received data is connected to a CLC014 equalizer that
reconstructs serial digital data from twisted pair transmission
lines. Its transfer function approximates the reciprocal of the
cable loss characteristic. The differential outputs, at PECL
logic levels, are connected to a S3016 receiver which provides
the first stage of digital processing to recover the SONET
STS-3 serial bit stream. A CMI decoder is then used for
decoding the STS-3 signals. Clock recovery is performed on
the incoming CMI coded data to regenerate a clock that is
frequency matched to the incoming data baud rate at the
SERDATIP/N differential inputs. The 19.44Mhz reference
clock is distributed to the S3016 to ensure correct internal
PLL start up and proper operation under loss of signal
conditions. An integrated prescaler and PLL circuit is used to
multiply this 19.44Mhz reference frequency to the nominal bit
rate of the 155.52Mb/s serial clock.
This Serial clock then passes through a programmable delay
circuit, so that the clock and data may be correctly timed, and
then translated from PECL to TTL by 10ELT21 circuits.
The output serial data is latched by a 10elt52 circuit and may
also be delayed by another programmable delay circuit before
being translated to a TTL level.
The circuit of receiver section is shown on page 33.
5
b) Altera_rx1 logic
Altera_rx1 consists of 3 parts and is described on pages 11 to
14:
- The shift register receives the serial data and performs a
conversion from serial data to a 25 bit parallel data word. Odd
parity bit checks are performed and the result is available in a
4bit OP<3..0> bus.
A signal parr_err is decoded from this bus and will be used as
status later. The IDLE bit is decoded from the input data and
latched by the rxclock.
- A down counter which divides the input clock by 25. The
linkready is also decoded in this section.
The rxclock1 block provides rx_latch_ce and status bits Rx_fifo_write_clock.
All the logic is integrated into an Altera EPM7064SLC84-5
PLD.
c) Altera_rx2 logic
Unfortunately 66 logic cells are necessary for building all the
receiver logic and the fastest Altera'PLD is a 5ns circuit but
contain only 64 logic cells, so we have been obliged to split the
logic into 2 PLDs.
The Altera_rx2 contain a register, which extracts the 20 bits
of rx_fifo_data followed by the 4 rx_fifo_parity error bits.
This logic is also integrated into an Altera EPM7064SLC84-5
PLD.
The circuit of the Altera_rx2 logic is shown on pages 15 and
16.
6
d) Rx_fifo
The Rx_fifo section is composed of 4 IDT 7206-20 (16k x 9)
CMOS parallel fifos from IDT and may be read by the VME
databus.
The Rx_fifo circuit is shown on page 32.
3. VME
VME section contains 5 blocks, which can be seen in pages 21
to 25.
-decoder
-controlstatus
-resetlogic
-datbuf
-rxtxfifos
The three Altera PLDs and fifos have been simulated using the
Cadence Design System at 178Mhz, which is the maximum
working frequency of the design.
4. CONCLUSION
7
4605163 cycles of 8190 words have been check (9.4 10.11 bits)
in random mode. Two parity errors have been founded during this
test.
The second transmission test has been made using 54 m of
another STP cable used during nomad experiment.
The transmission of 8190 words, in random mode, has been send
during 160 hours that represent 1.76. 10.12 bits sending without
any error.
Another test have been made with 50 m of UTP 4 pairs cable
from ALCATEL with a very good result 24676500 cycles with
8000 words (4.9 10.12 bits) in random mode.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
/* This SCL file was generated with Resolution of 0.100 */
HISTORY 50000
OPEN 'CLK155TX';
ASSERT 'CLK155TX', 0-32 (6.4,64);
OPEN 'CLK155RX';
ASSERT 'CLK155RX', 0-11, 43-65 (6.4,64);
/* VME PART*/
OPEN 'PWONRST';
DEPOSIT 'PWONRST', 0+0 1+10 0+5000;
OPEN 'SYS_RST*';
DEPOSIT 'SYS_RST*', 0+0 1+10;
OPEN 'CNTRL_RST';
OPEN 'RST_ERR';
OPEN 'RST*';
OPEN 'ADD<23..16>';
DEPOSIT 'ADD<23..16>', $xU+0 $xB+12000 $xA+16000;
OPEN 'BASE_ADD<20..17>';
DEPOSIT 'BASE_ADD<20..17>', $x5+0;
OPEN 'AM<5..0>';
DEPOSIT 'AM<5..0>', $xU+0 $x39+12000;
OPEN 'AS*';
DEPOSIT 'AS*', 0+0 1+10 0+12400 1+14800 0+16500 1+19500 0+22500 1+24500 0+27500
1+29500 0+33000 1+35500;
OPEN 'VME_DATA<31..0>';
DEPOSIT 'VME_DATA<31..0>', $xU+0 $x3+12000 $xU+15000 $x12345+16500 $xU+20000
$x85432+22000 $xU+25000;
OPEN 'WR*';
DEPOSIT 'WR*', 0+0 1+10 0+12000 1+15000 0+16500 1+19000 0+22000 1+25000;
OPEN 'DS0*';
DEPOSIT 'DS0*', 0+0 1+10 0+12400 1+14000 0+16500 1+18300 0+22500 1+24000
0+27500 1+29000 0+33000 1+35000;
OPEN 'DS1*';
DEPOSIT 'DS1*', 0+0 1+10 0+12400 1+14000 0+16500 1+18300 0+22500 1+24000
0+27500 1+29000 0+33000 1+35000;
OPEN 'TIM_ACK';
OPEN 'TIM_CNTRL_RST';
OPEN 'TIM_RST_ERR';
OPEN 'ACK';
OPEN 'TDTACK*';
/* TX_FIFO PART*/
OPEN 'TX_FIFO_EMPTY*';
OPEN 'TX_FIFO_FULL*';
OPEN 'TX_FIFO_DATA<20..1>';
OPEN 'TX_FIFO_RCLK*'
OPEN 'TX_FIFO_WCLK*';
OPEN 'CNTRL_SEND';
OPEN 'SER_OUT';
/* RX_FIFO PART*/
OPEN 'RX_FIFO_WCLK*';
OPEN 'RX_FIFO_RCLK*';
OPEN 'RX_FIFO_DATA<20..1>';
OPEN 'RX_FIFO_FULL*';
OPEN 'RX_FIFO_EMPTY*';
OPEN 'RX_BURST_READY';
OPEN 'LINK_READY';
OPEN 'BURST_SYNC_ERR';
OPEN 'BURST_OVERFLOW';
OPEN 'BURST_PAR_ERR';
SIM 50000;
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The next picture represents the result simulation when one word
(12345) is sending from VME databus to the tx_fifos, on the
ser_out signal the word is encoding and is available on the
rx_data bus.
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