General Purpose FIFO
on Virtex-6 FPGA ML605 board
Students:
Oleg Korenev
Eugene Reznik
Supervisor:
Rolf Hilgendorf
1
Semester: spring 2012
Content
1.
2.
3.
4.
Project overview
Goals
Motivation
Specifications
5. Block Diagram
6.
7.
8.
9.
Initial steps
Possible solutions
Workflow
Timeline
2
Project Overview
• Design and implementation of General Purpose FIFO which
allows usage of external memory(DDR III) as FIFO storage on
Xilinx FPGA device
• Design and implement generic IP core of FIFO
• Design and implement GUI generator of IP core on PC
• Create design which serves as sample application
3
Our goals
• Gain experience in hardware development
(VHDL environment)
• Explore and expertise FPGA work environment
• Create design with configurable
• word size
• FIFO size
• bandwidth
• Achieve best performance
• Minimize usage of FPGA resources
• Make our world a better place
4
Motivation
•Why do we need big FIFO?
• FPGA works relatively fast comparing to data
transmission rate. So we need special storage to
accumulate pre-processed and processed data.
• Xilinx provides us with standard and relatively small
FIFO (cores).
• In case we need to process big chunks of data we will
have to use big storage (FIFO).
For example in signal processing.
5
Specifications
• Hardware
• Xilinx Virtex-6 ML605 FPGA Evaluation Kit
• DDR III memory
• Ethernet interface
• UART interface
• PC with Ethernet interface
• Software
• ISE Design Suite Logic Edition Version 13.2
• PlanAhead Design and Analysis Tool
• ISIM/Modelsim
6
Block Diagram
Host FIFO region
User Logic FIFO area
User Logic FIFO region
Memory Controller
Virtex 6
AXI bus
FIFO
Host connection: ETHERNET/UART/PCIe
Host PC
FIFO IN
User Logic FIFO controller
FIFO OUT
FIFO OUT
FIFO IN
Host FIFO controller
CONTROLLER
Memory Arbiter
User
Logic on
FPGA
7
Initial steps
• External interface
•
•
•
•
Define FIFO interface
Define word size limitation and its connection to bandwidth
Choose external memory interface
Choose host data exchanging interface
• Internal architecture
• Define memory arbiter functionality
• Define main controller functionality
• Define host and user logic FIFO controllers functionality
8
Possible solutions
• Choose data exchanging interface
• Ethernet
• UART
• PCIe
• Choose external memory interface
• AXI interface
• Native interface
• User interface
• Max word size
• 128 bits
• Greater than 128 bits
9
Workflow
•
•
•
•
Studying memory controller
Studying usage of Ethernet for communication with PC
Studying and generating standard FIFO with internal RAM
Implementation generalized FIFO controller
•
•
•
•
Implementing User Logic controller
Implementing Host FIFO controller
Implementing memory arbiter
Implementing main FIFO controller
• Verification of design
• Implementing GUI for generating FIFO IP core
• Implementing sample design
10
Timeline
Task
Duration
Studying to integrating and interfacing with memory
controller
1 week
Studying to integrate internal FIFO and defining User
Logic FIFO interface
1 week
Studying communication with PC through Ethernet
1 week
Midterm Presentation
1 week
28/4
5/5
12/5
11