Supplemental Information
Ge Nanowire growth details:
Ge nanowires were engineered to grow in <110>-type directions using a guiding structure whose
fabrication started with a SOITEC, (001)-oriented, silicon-on-insulator (SOI) substrate. The SOI
wafer had three layers: (1) a 100 nm, (001)-oriented, n-type, Si device layer on top of (2) a 200
nm, buried oxide layer (BOX) on (3) a p-, (001)-oriented, Si handle wafer. The basic fabrication
of the structure is described here and more details can be found in Reference 9 and 10. Si3N4
was deposited on the device layer surface and etched with the pattern aligned along a <110>
direction of the underlying Si device layer. The remaining Si3N4 was then used as a hard mask
to etch the underlying Si with KOH to reveal Si {111}-type planes and stop at the SiO2 surface
(see figure S1a). Etching the Si formed electrically isolated mesas for electrical characterization
of nanowires grown between the mesas as described below. After etching the Si, another layer
of Si3N4 was deposited and anisotropically etched to retain Si3N4 on the Si-{111} sidewalls.
The Si and Si3N4 were then used as masks for a buffered-oxide etch to undercut the top, Si,
device layer.
Au was selectively placed on exposed Si using a blanket deposition, an alloying-anneal, and a
field-etch procedure, shown schematically in figure S1b. Blanket Au catalyst nanoparticle
deposition was accomplished by exposing the structure to 3 parts unconjugated, Au colloid
(supplied by Ted Pella and containing 100 nm diameter, Au nanoparticles) and 2 parts of 5% HF.
The sample was annealed at 400 ◦C —above the 363 ◦C Au/Si eutectic temperature—in a H2
ambient so that those Au nanoparticles in contact with Si alloyed with the Si. Au nanoparticles
on the oxide and nitride surfaces did not alloy with Si and were then removed by etching some of
the oxide and nitride in BOE and 155 ◦C H3PO4, respectively. This field etch removed stray
nanoparticles and resulted in Au remaining on exposed Si surfaces (namely, the underside of the
Si device layer).
The Au nanoparticles were then used as catalysts for Ge NW growth. The sample was annealed
again for 10 min at 700 oC at 95 Torr while flowing 1 slm H2. Ge nanowires were grown for 30
min at 337 ◦C under the following conditions: 1 slm H2, 95 sccm 2% GeH4 balance H2, at 95
Torr (figures S1c and S1d). After the nanowires were grown, the sample was dipped in Transene
TFA gold etch:HCl::9:1 for 2 min to remove the gold nanoparticles.
Description of the adjacent growth process:
Figure S2 shows the interaction of three, surface nanowires which grow laterally over the SiO2
surface and begin the process of covering the SiO2 surface with single-crystalline Si. The three
nanowires are depicted over the SEM image as arrows in three different colors, black, blue and
green. The numbers by the beginning of each arrow indicate the sequence in which the nanowire
grew. For example, in the case of the nanowire described by the blue arrow, the nanowire
originated near the blue number “1” and grew towards the bottom left of the figure. (In every
case, the color coded number addresses the arrow of the same color, the beginning of which is
closest to the number itself.) The nanowire then encountered the top-Si layer and then made a
180o turn to grow back upon itself following the blue arrow labeled with a blue “2.” Then, the
nanowire turned 90o to the left and followed the blue arrow labeled “3.” In a similar manner, the
other two, black and green, nanowires’ growth process is described by numbers and arrows. The
inset of the figure depicts a larger area where one can see the nucleation points of the black and
blue nanowires on a different top-Si layer.
Schematic of a partial amorphous cap:
Figure S3 depicts the process described in Figure 2 with the addition of an oxide layer covering
the semiconductor growth. This oxide cover may be required to keep the growth planar, against
the substrate surface. This process is similar to what was done in reference 14 in which a Si
nanowire grew thru a small channel whose walls were made with SiO2. This type of structure
may not be able to be made easily with all SiO2, however, if the top-amorphous layer was made
of a different material, say Si3N4, one could use selective etch chemistry to make this structure.
Figures
Figure S1
Figure S2
Figure S3