Superlattice-Source Nanowire FET with Steep
Subthreshold Characteristics
MOt
Es
MASSACHUSETTS
OF TECHNOLOGY
Xmn Zhao
JUL 012013
B.S. Physics
Peking University (2010)
....
Submitted to the Department of Materials Science and Engineering
in Partial Fulfillment of the Requirements for the Degree of
Master of Science in Materials Science and Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2012
C2012 Massachusetts Institute of Technology
All Rights Reserved.
A uth or ...............................................
.........
........................................................
Department of Materials Science and Engineering
August 30, 2012
C ertified by ............................................................................................................................
Jesn's A. del Alamo
Professor of Electrical Engineering
Thesis Supervisor
A n d b y .................................................................................
...............................................
Silvija Grade'ak
Associate Professor of Materials Science and Engineering
Thesis Reader
Accepted by .......................................
.......................
Gerbrand Ceder
Chair, Department Committee on Graduate Students
ENSTTU
2
Superlattice-Source Nanowire FET with Steep
Subthreshold Characteristics
by
Xin Zhao
Submitted to the Department of Materials Science and Engineering on August 30, 2012
in Partial Fulfillment of the Requirements for the Degree of Master of Science in
Materials Science and Engineering
Abstract
The non-scalable room temperature 60 mV/dec subthreshold swing of a conventional MOSFET
is a fundamental limit to the continuation of transistor power scaling. In order to further reduce
transistor power consumption and transistor footprint, new subthreshold transport mechanisms
other than thermionic emission over an energy barrier are required.
In this thesis, we devote our efforts towards the analysis and demonstration of a superlatticesource nanowire FET which can potentially beat the 60 mV/dec limit. This key to this device
concept is to engineer the density of states of electrons at the source via a superlattice. We have
calculated the band structure of a superlattice using a self-consistent quantum-mechanical
simulation environment. In particular, the effect of transversal confinement on the band
structure of a superlattice that occurs in a nanowire has been studied. We show that in order to
obtain single-subband conduction, semiconductor nanowires with sub-10 nm diameter have to
be fabricated. An analytical expression of the subthreshold swing including the effect of band
edges has been derived and good agreement with simulations was achieved.
A process flow to fabricate III-V nanowire MOSFETs has been designed. We have developed
several key aspects of this process and have demonstrated the capability of fabricating smooth
high-aspect ratio sub-10 nm semiconductor pillars in the InGaAs/InAlAs system lattice matched
to InP.
Thesis Supervisor: Jesn's A. del Alamo
Title: Professor of Electrical Engineering
3
4
Acknowledgments
First and foremost, I would like to express my deepest gratitude to my thesis advisor, Prof.
Jesn's A. del Alamo for offering me this great opportunity to work on this exciting project. His
dedication to excellence, strong physical sense of device physics and brilliant vision of this
research field have constantly inspired and motivated me. Besides the scientific knowledge and
technical skills I have learned from him, I benefit a lot from his elegant yet strict way of
conducting research. He is a role model for successful researchers. I am very grateful for this
excellent supervision and persistent help.
I also want to thank Prof. Dimitri Antoniadis for his sharp, smart comments and suggestions
during the group meetings. I have greatly benefited from his expertise and thinking each time I
interact with him.
This thesis would have not been possible without support from my colleagues and friends. I
would like to sincerely thank Jianqiang Lin, Ling Xia and Winston Chem, for getting me started
with III-V processing, simulation and measurements. I also want to say thank you to Luke Guo
and Tao Yu. Discussions with them really spark new ideas and thoughts. Many thanks to del
Alamo group members: Donghyun Jin, Alex Guo, Shireen Warnock, Jungwoo Joh, Tae-woo
Kim and Usha Gogheni. I also appreciate the help from Fitzgerald group students Adam Jandl,
Ryan Iutzi and Palacios group student Bin Lu, Han Wang and Omar Saadat. I shouldn't forget
other folks on the
6 th
floor too.
I am also indebted to students and professors affiliated with the Center for Energy Electronics
Sciences. Especially, I would like to thank Sapan Agarwal for insightful discussions on
problems in TFETs. I have also benefited a lot from Amit Lakhani's advice on processing.
This research was sponsored by the Center for Energy Efficient Electronics Sciences, which
receives supportfrom the NationalScience Foundation.
5
6
Contents
L ist o f F igu re s ...............................................................................................................................................
9
L ist of T ab le s ..............................................................................................................................................
13
Chapter 1IIntroduction ................................................................................................................................
15
1.1
The Need for Low Power Electronics...................................................................................
15
1.2
The Limit of Current Transistors .........................................................................................
16
1.3
Superlattice-Source Nanowire FETs with Steep Subthreshold Characteristics ....................
18
1.4
T h esis O u tlin e ...........................................................................................................................
19
Chapter 2 Device Concept of Superlattice-Source Nanowire FETs ........................................................
21
2 .1
In tro du ctio n ...............................................................................................................................
21
2.2
Operation M echanism of Superlattice-Source Nanowire FETs .............................................
21
2.2.1
Physics of the Subthreshold Current in M OSFETs......................................................
21
2.2.2
The Concept of Engineering the DOS at the Source......................................................
22
2.2.3
Superlattice as Energy Filter .........................................................................................
24
Quantum Mechanical Simulations of the Band Structures of Nanowire Superlattice ..........
27
2.3
2.3.1
Nextnano Simulation of the Band Structure of Superlattice ........................................
2.3.2
The Effect of Transversal Confinement on the Band Structure of Superlattice............. 29
2.4
Device Design Issues ................................................................................................................
27
32
2.4.1
Possible Device Architectures .......................................................................................
32
2.4.2
Number of Periods of Superlattices ..............................................................................
34
2.4.3
Superlattice Doping...........................................................................................................
37
7
2.4.4
M aterial System ................................................................................................................
39
2.4.5
Non-idealities in the Subthreshold Regime...................................................................
42
2 .5
Su mm ary ...................................................................................................................................
Chapter 3 Technology for SLS nanowire FETs.....................................................................................
43
45
3.1
Introduction...............................................................................................................................
45
3.2
Overall Process Design.............................................................................................................
45
3.3
Process Technology ..................................................................................................................
47
3.3.1
Electron Beam Lithography.........................................................................................
47
3.3.2
Reactive Ion Etching.....................................................................................................
55
3.3.3
Digital Etch .......................................................................................................................
63
3.3.4
Planarization .....................................................................................................................
66
3 .4
S u mm ary ...................................................................................................................................
Chapter 4 Conclusions and Suggestions ................................................................................................
68
69
4 .1
S u mm ary ...................................................................................................................................
69
4.2
Suggestions ...............................................................................................................................
70
4.2.1
Ongoing Research Efforts ................................................................................................
70
4.2.2
Suggestions for future research..........................................................................................
71
B ib liog rap hy ...............................................................................................................................................
8
73
List of Figures
Figure 1-1. US electricity use for date centers (Figure taken from [1]).................................................
15
Figure 2-1 (Left) Distribution of electrons in the source of an n-MOSFET. (Right) Electrons in the high
energy tail of the electron energy distribution at the source contribute to subthreshold current........... 22
Figure 2-2. a. The imaginary band structure at the source consists of minibands and minigaps. b.
Conduction band diagram of the device biased in the subthreshold regime where electrons from the first
miniband are suppressed by the energy barrier. c. Conduction band diagram of the device biased in the
on sta te ......................................................................................................................................................
23
Figure 2-3 (Left) Simulated subthreshold characteristics of a nanowire FET with imaginary ideal band
structure at the source showing very steep swing. D is the nanowire diameter. Ns is the source doping
level, AEc is the extension of the conduction band (Figure taken from [5])........................................ 24
Figure 2-4. a. Superlattice formed by alternating GaAs/AlAs layers and the corresponding potential
energy profile (Figure taken from [2]). b. Allowed minibands (the shaded area) calculated as a function
of well or barrier width and the corresponding potential energy profile (Figure taken from [2]). c.
Schematic illustration of minibands and minigaps with regard to the original conduction band structure.
..................................................................................................................................................................
25
Figure 2-5. Schematic illustration of simulated nanowire FET and conduction band diagram of
superlattice (Figure taken from [7])..........................................................................................................26
Figure 2-6. Subthreshold characteristics normalized to diameter for different SL material pairs. (Figure
tak en fro m [7 ])..........................................................................................................................................
26
Figure 2-7. Calculated first and second eigenstate/eigenenergy with respect to the conduction band
profile for G aA s/A lGaA s superlattice...................................................................................................
28
Figure 2-8. Calculated band structure for GaAs/AlGaAs superlattice, including the Ist, 2 nd miniband and
the m inigap in b etw een .............................................................................................................................
28
Figure 2-9. Calculated band structure for 2.94 nm InGaAs/ 1.18 nm InAlAs superlattice along the growth
direction. In the perpendicular direction, electrons are confined to a square with a side of 7 nm...... 30
Figure 2-10. Zoom-in of figure 2-9 showing the first three subbands more clearly. The energy separation
betw een the first and second subband is 120 m eV . ...............................................................................
31
Figure 2-11. The energy separation between the first and second band versus nanowire cross-section
dimension for otherwise the same superlattice in Figure 2-9 and 2-10. ...............................................
31
9
Figure 2-12. a. Cross-sectional distribution of electron density in the InGaAs nanowire with side length
of 30 nm and 50 nm at VGS-VT= 1.2 V. b. Normalized electron distribution at the middle of the nanowire
for square-shape Si and InGaAs nanowires. (Figure taken from [8])..................................................
33
Figure 2-13. Diagram of the proposed superlattice source nanowire FET. ..........................................
34
Figure 2-14. Conduction band diagram when device is biased in the subthreshold regime a. The
imaginary minibands that have infinitely sharp band edge. b. Real minibands formed by a superlattice
with finitely sharp band edge....................................................................................................................
35
Figure 2-15. a. Conduction band diagram for the 10 periods of InGaAs/InAlAs superlattice simulated. a.
Ballistic transmission probability calculated for 7 and 10 periods of superlattice................................ 38
Figure 2-16. Simulated transfer characteristics for different periods of superlattice. Wire diameter D=
5nm, EOT= m. Superlattice is comprised of 1.59 nm GaN/ 0.95 nm AlGaN (Figure taken from [6]) 39
Figure 2-17. (Left) Simulated transfer characteristics for SLS nanowire FETs with different gate lengths
and doping levels in the SL region. The values were labeled in the figure. (Right) Conduction band
profile of the simulated devices for various gate voltages (Figure taken from [4])............................
40
Figure 2-18. (Left) On/off current ratio (top) and ION (bottom) vs. IOFF - ON was calculated at VDSO -1 V
and VGSgO.4 V. (Right) Peak and average S (top) and gate voltage ranges over which the peak and
average S are stable (bottom). From (A) to (F), doping level increases from 2 to 1019 cm-3, with a step of
10'9 cm -3 . (F igure taken from [6]).............................................................................................................
41
Figure 3-1. Process flow of SLS nanow ire FETs...................................................................................
46
Figure 3-2. The heterostructure used in this work. All layers are lattice matched to InP...................... 48
Figure 3-3. Top view SEM images of the HSQ line structures defined following the same process flow,
except that a Si adhesion layer was evaporated onto the substrate in (b). .............................................
50
Figure 3-4. 150 tilted SEM image of the dot pattern with a drawn diameter for 30 nm. The dose time was
0.6 and 0.38 for the left and right figure, respectively.........................................................................
52
Figure 3-5. 15' tilted SEM image of the dot pattern with a drawn diameter of 15 nm.............
53
Figure 3-6. 150 tilted SEM image of the dot pattern with drawn diameters of 30nm and 600 nm. The
sidew all profile for 600 nm w as m ore sloped.......................................................................................
53
Figure 3-7. Top view SEM image of the dot pattern exposed with Elionix (left) and with Raith (right),
follow ing the process flow shown in Table 3-1 ....................................................................................
54
10
Figure 3-8. 150 tilted SEM images of semiconductor pillars with different sizes after a 2 minute etch
following parameters given in Table 3-5. The drawn HSQ mask size was 20 nm, 40 nm, and 200 nm
respectively (from the left to the right) ................................................................................................
57
Figure 3-9. 150 tilted SEM images of semiconductor pillars etched with parameters specified in Table 36. The HSQ mask thickness was 90 nm for all three cases...................................................................
58
Figure 3-10. 450 tilted SEM images with regard to the top view of the semiconductor surface etched with
parameters specified in Table 3-7. No hard mask was defined by EBL for both cases, since only surface
prop erties w ere ex am ined .........................................................................................................................
60
Figure 3-11. 150 tilted SEM image of a semiconductor fin etched with a 30 nm wide HSQ line. The
param eters for etching were given by Table 3-5..................................................................................
61
Figure 3-12. 150 tilted SEM image of semiconductor pillars etched with HSQ dot of 200 nm in diameter.
The param eters for etching were given by Table 3-8. ..........................................................................
62
Figure 3-13. 150 tilted SEM image of semiconductor pillars with 30 nm Molybdenum layer evaporated
onto the heterostructure shown in Figure 3-14. (left) immediately after RIE process (right) after 8 cycles
of wet digital etching, with 30% H2O as the oxidant and 49% HF as the oxide etchant..................... 65
Figure 3-14. The heterostructure grown on GaAs substrate used for Figure 3-13.................................
65
Figure 3-15. 150 tilted SEM image of semiconductor pillars with the heterostructure shown in Figure 3-2.
(left) immediately after RIE process (right) after 7 cycles of dry digital etching, withl0% H2 S0 4 as the
o x id e etch an t.............................................................................................................................................6
6
Figure 3-16. (left) Cross-section SEM image after planarization process described in Table 3-10 was
applied to a semiconductor fin (right) 150 tilted SEM image of the same position. ..............................
68
11
12
List of Tables
Table 2-1. Well (w) and barrier (b) thickness for the four material pairs simulated. (Data taken from [7]).
..................................................................................................................................................................
26
Table 2-2. Comparison of calculated band parameters of three types of AlGaAs/GaAs superlattices with
a barrier thickness of 2.5 nm and various well thicknesses between literature ([3], in black) and
N extnano sim ulation s (in red)...................................................................................................................
29
Table 3-1. Optimized process flow for EBL using HSQ resist............................................................
50
Table 3-2. Thickness range of HSQ with different solid concentration, at typical spin speed .............
51
Table 3-3. The right doses for different drawn dot sizes .......................................................................
53
Table 3-4. Process flow for 02 plasma anneal to harden the HSQ as the etch mask .............................
54
Table 3-5. Optimized SAMCO ICP RIE parameters...........................................................................
56
Table 3-6. SAMCO ICP RIE parameters for the etch results shown in Figure 3-9 (a), (b) and (C)......... 59
Table 3-7. SAMCO ICP RIE parameters for the etch results shown in Figure 3-9...............................
60
Table 3-8. Plasmaquest ECR RIE parameters for the etch results shown in Figure 3-12.....................
63
Table 3-9. D igital etching process details..............................................................................................
64
Table 3-10. SO G planarization process details ....................................................................................
67
13
14
Chapter 1 Introduction
1.1 The Need for Low Power Electronics
Power consumption is becoming of one of the major concerns in modern electronics. Reducing
the power consumption of electronics can make a significant impact on the worldwide energy
demands. Specifically, in 2010 data center alone consumed about 2% of all the electricity in the
United States, as shown in Figure 1-1 [1]. The thriving of portable electronics further
necessitates the reduction of power consumption as batteries of smart phones can barely last for
a day.
140
3.5%
130
120
110
100
Percentages refer
to % of US
electricity use in a
given year
Current
range
2.8%
90
2.2%
80
70
0
1.5%
60
Cooling +
power
distribution
50
:)
40
-
30
%oinfrastructure
UCommunications
a3Storge
20
IT load
OHigh-nd servers
Mid-range servers
10
EVolume servers
0
2000
2005
Best Upper Lower
All
trends guess bound bound
cont.
2007
2010
1
Figure 0-1. US electricity use for date centers (Figure taken from [1])
In addition to this, Si MOSFETs scaling has recently entered an era of 'power-constrained
scaling' as the power density dissipated by logic chips hit about 100 Wcm
2
, which is
practically limited by packaging and cooling costs [9]. Continued progress in transistor density
will require a reduction in the operating voltage, but this will compromise the switching speed.
The introduction of a new channel material in which charge carriers travel at a much higher
velocity than in silicon could allow a reduction in voltage without a loss of performance.
However, even MOSFETs with new channel materials are subject to the fundamental limit
described below. Future scaling beyond that requires innovation in device concept.
1.2 The Limit of Current Transistors
The fundamental reason that the operating voltage has stopped scaling is because conventional
MOSFETs rely on thermionic injection of carriers over an energy barrier [10]. Subthreshold
swing, S, defined as the gate voltage required to change the drain current by a decade when the
transistor is operated in the subthreshold region has a fundamental limit of 60 mV/dec at room
temperature, which is non-scalable. Typical values in advanced Si CMOS technology are close
to 100 mV/dec. In order to significantly reduce the operating voltage while maintaining an
adequate on-off ratio, the subthreshold swing must be reduced.
New physical mechanisms are needed beyond thermionic injection to overcome this
fundamental limit and obtain a subthreshold swing smaller than 60 mV/dec. To this regard,
there have been extensive research efforts going on worldwide and several interesting device
concepts have been proposed and demonstrated, including impact-ionization MOSFET (i-MOS)
[11], the negative capacitance FET [12], the nano-electromechanical relay (NEM relay) [13, 14],
and the tunnel FET (TFET) [15]. While showing promising device characteristics, all these new
concepts have their own limitations.
The i-MOS FETs achieve steep turn-on by a positive feedback mechanism where a rise in the
drain current results in further current increase by lowering the threshold voltage through the
generation of minority carriers by impact ionization at the drain side. In order for significant
impact ionization to occur, a substantial voltage (larger than Eg/q, E. being the channel
16
material band gap) has to be applied as the drain bias, which tends to defeat the purpose of
operating voltage scaling [16]. While new channel materials featuring narrow band gap such as
InAs seems appealing, it is not clear if the problem can be solved considering the fact that in a
scaled quantum-well III-V FET, the channel has very strong quantization. Another concern is
that as modern transistors start to approach ballistic transport, impact ionization will be less
prominent as gate length scaling progresses[16]. Also, the transistor could have significant
additional delay as avalanche multiplication inherently takes time to build up [17], which limits
its use in logic applications.
The negative capacitance FET is another example which involves positive feedback mechanism.
The insulator between gate and channel in conventional MOSFET is replaced by a ferroelectric
material, whose permanent field will change in response to the amount of charge on the gate
capacitor, providing additional charges to the channel and hence higher current. Replacing the
gate oxide with a ferroelectric insulator raises severe fabrication, contamination and scalability
problems, and ferroelectric materials are again subject to fatigue-related degradation [12].
NEM relay is interesting as it realizes zero leakage current and infinitely sharp turn on
characteristics by physically separating the conductive components of the transistor in the offstate. Reliability, operating voltage, which is closely tied to energy efficiency and the speed will
benefit from miniaturization just as the Si CMOS. However, the mechanical switching delay is
orders of magnitude larger than its electrical counterpart, and complex circuit topologies where
a logic function is implemented using several relays in a single gate have to be used [18]. Due
to the large surface adhesion force that has to be overcome to turn on the device, the path to
minimization of operating voltage is yet to be demonstrated [19]. Also, contact reliability issues
such as vulnerability to wear, microwelding and surface oxidation has to be dealt with.
TFET conducts current by carriers tunneling through a barrier rather than flowing above it. The
conduction and valence band edges effectively filter the electrons tails with high energy which
cause the 60 mV/dec limit in conventional MOSFETs. TFETs usually suffer from the inability
to deliver high drive currents comparable to MOSFETs [20, 21] due to the large tunnel barrier.
Recently impressive drive currents [22-24] have been demonstrated using high quality III-V
17
heterojunctions which reduces the tunnel barrier significantly, but these devices have so far
failed to realize sub-thermal subthreshold swing. High drive current with steep turn-on
characteristics is still to be demonstrated.
1.3 Superlattice-Source Nanowire FETs with Steep
Subthreshold Characteristics
In this research we focus on a new device concept which involves a superlattice acting as an
energy filter at the source of a FET. As stated in the last section, carriers at the source with
higher than the source/channel barrier are responsible for the 60 mV/dec thermal limit of the
subthreshold current due to their Maxwellian distribution. In order to overcome this limit, one
possibility is to filter out the high energy electron tail. In TFETs, this filtering capability is
realized by aligning the source/channel energy bands. Only carriers lying in the energy window
of the overlap between source/channel band edges can contribute to the current, while high
energy carriers are effectively cut off by the band edges.
Rather than solely relying on tunneling effect, another scheme is to insert a superlattice region
in the source. It is well known that the band structure of a superlattice is comprised of
minibands (where the DOS is large) and minigaps (where the DOS is low) whose energy scale
is on the order of several tens to hundreds of meV. By accurately selecting the constituent
materials and by adjusting the superlattice physical dimensions, a superlattice region inserted in
the source can filter out the carriers in the subthreshold and off-state by minigaps, thus resulting
in steep turn-on characteristics. The device can possibly deliver a drive current that is
comparable to that of MOSFETs when the miniband is properly aligned with the channel in the
on-state. The concept was first proposed by Bjoerk et al. [25] and later investigated theoretically
by Gnani et al [6, 7, 26], who showed promising performance.
A nanowire design and a wrap-around-gate are also essential elements of this device concept for
the following reasons. Short-channel effects resulting from the sharing of the electrical charges
in the channel region between the gate and the source/drain limit continued transistor scaling of
the planar design below around 20 nm in gate length [27]. Multigate architectures can provide
18
stronger gate control that mitigates short-channel effects, and thin nanowire with a wraparound-gate is one of the most promising designs. A strong gate control is one of the keys to
obtain a steep device turn-on. Another possible benefit from thin nanowire design is the volume
inversion effect. In a nanowire with a diameter below a few tens of nanometers, it is possible
that transport properties in the inversion region will improve as nanowire is further thinned
down [8]. This is in contradiction to the expectation that reducing the nanowire size will
degrade transport due to the relative increase in surface roughness scattering given the larger
surface to volume ratio. The main reason is the increased quantum confinement at smaller
dimensions which pushes the inversion carriers further away from the interface and thus are less
affected by the roughness scattering.
1.4 Thesis Outline
In this research, we aim to understand the key device design issues for a new superlattice-source
nanowire FET with steep subthreshold characteristics. Towards this end, we develop a quantum
simulation environment to calculate the DOS of nanowire superlattices. The thesis also focuses
on technology development for the top down fabrication of vertical nanowire FETs with a
diameter less than 20 nm and experimental probing the DOS of nanowire superlattices. The
thesis will be organized in the following way.
Chapter 2 will start with the operation mechanism of SLS nanowire FETs by reflecting on the
MOSFETs limit and explaining the concept of engineering the DOS at the source through a
superlattice acting as an energy filter. Following this, a brief introduction to the basic theory of
superlattices will be presented, and our simulation environment using a Poisson-Schr6dinger
solver (Nextnano) for band structures calculations will be introduced and calibrated with data
from literature. Next, we will use the calibrated simulation tool to study the effect of lateral
confinement imposed by a nanowire configuration on the band structures of a superlattice. The
chapter will end with discussions on several device design issues including the choice of
materials system, possible transistor architectures, nanowire dimensions, etc.
19
In Chapter 3, we first describe the process flow designed to fabricate III-V nanowire MOSFETs.
Key fabrication technologies developed will be detailed. Finally, the summary of this thesis are
presented in Chapter 4, together with ongoing research efforts and suggestions for future work.
20
Chapter 2 Device Concept of Superlattice-Source
Nanowire FETs
2.1 Introduction
This chapter introduces the device concept of superlattice-source nanowire FETs (SLS
nanowire FETs). The operation mechanism will be presented, followed by quantum mechanical
simulations of the band structure of the superlattices. Several design issues related to the
realization of the steep turn-on will be discussed.
2.2 Operation Mechanism of Superlattice-Source
Nanowire FETs
2.2.1 Physics of the Subthreshold Current in MOSFETs
In a conventional MOSFET, the leading dependence of the subthreshold current can be
understood as the thermionic injection of carriers over the source/channel energy barrier [10].
Let's take an n-MOSFET as an example: the electron distribution at the source is given by
n = fE g (E)f(E)dE
(2.2)
g (E) oc V-
f(E)
=
exp
kT
(2.1)
)
+ 1)
(2.3)
The shape of the distribution is shown on the left of Figure 2-1, which has an exponential tail. In
the subthreshold regime, the current is contributed by electrons that possess energies larger than
the source/channel barrier, as shown on the right of Figure 2-1. Following equation (2.1), the
density of this electron tail can be expressed as
ntaii =
f
o g(E)f(E)dE
(2.4)
where <ps is the surface potential in the channel. The integral is determined by the Fermi-Dirac
distribution function f(E), as it exponentially decays with energy while density of states g(E)
21
only increases in a square root form. In this way, the density and thus the current is proportional
to exp
(-
q
, where
kT
k
q
is the thermal voltage. Subthreshold swing, S, which is defined as the
gate voltage required to change the drain current by one order of magnitude, can be expressed as:
dos
dVG
S =n
d4ps d(log1 0 ID)
mV
U
x n10 -=n x 60Odec
q
(2.5)
T = 300K
In this expression, n is the ideality factor and it represents the degree of control of the surface
potential by the gate. The closer to 1 n is, the tither the gate control over the channel. At room
temperature, the subthreshold swing of a MOSFET is 60 mV/dec at best. Typical values of S in
advanced CMOS technology are close to 100 mV/dec; by lowering VDD from 500 mV to 250
mV while preserving the overdrive (this requires lowering the threshold voltage by the same
amount), the leakage power has been shown to increase unacceptably by a factor of 275 in a 45nm bulk CMOS technology [28].
E
High energy tail +
Subthreshold current
High-energy tail of
source electrons
--
g (E)f (E)-
----
g (E) oc E2f
Ec
.g(E)
Figure 0-1 (Left) Distribution of electrons in the source of an n-MOSFET.
(Right) Electrons in the high energy tail of the electron energy distribution at the
source contribute to subthreshold current.
2.2.2 The Concept of Engineering the DOS at the Source
To overcome the 60 mV/dec limit, let's examine equation (2.1) more carefully. The FermiDirac factor will always be there as long as we have carriers. If we can find a way to filter out
22
the electron tail at high energy by modifying the density of states in the source, there is a
possibility that the subthreshold current will be suppressed and the subthreshold swing will be
steeper.
Suppose rather than a single conduction band extends all the way up for a n-MOSFET, we have
a band structure where minibands which have extension of a few hundreds of meV are separated
by minigaps that have similar energy scale, as shown in Figure 2-2a. When the upper edge of
the first miniband at the source contact is lower than the energy barrier at the virtual source, the
electrons in this band will be blocked from conduction. Since the second miniband is separated
by a significant minigap, there will be few electrons available and hence the subthreshold
current will be effectively suppressed. Figure 2-2c suggests that, on the other hand, as soon as
the upper edge of the first miniband is lined up with the channel potential, the current will rise
very fast assuming a perfect band edge.
b
a
E
92 (E)~~
Empty
miniband
Minigap _
Partially filled
miniband
(E)f(E)
(
ggCE
(E )
>
g(E)
Figure 0-2. a. The imaginary band structure at the source consists of minibands
and minigaps. b. Conduction band diagram of the device biased in the subthreshold
regime where electrons from the first miniband are suppressed by the energy
barrier. c. Conduction band diagram of the device biased in the on state
23
In the simulation performed by Gnani et al [5], the source of the nanowire FET features similar
band structure with perfect band edges, showing a very steep slope of 3 mV/dec, which is in
fact due to direct source to drain tunneling (Figure 2-3).
2.2.3 Superlattice as Energy Filter
It's well known that the band structure of a superlattice is comprised of minibands and minigaps
[29], and probably can serve the purpose of a proper energy filter to engineer the density of
states at the source. As shown in Figure 2-4a [2], a superlattice is formed by alternating layers
of two semiconductors with different band gaps. In addition to the periodic potential of the
crystal lattice, an additional one-dimensional potential, the period of which significantly
exceeds the lattice constant, is present. As a result of the addition of this potential to the crystal
potential, the original conduction band breaks into minibands and minigaps, as shown
schematically in figure 2-4c (an equivalent point of view is that single quantum levels within
the material with smaller band gap extend to different minibands, illustrated by Figure 2-4b).
3 mV/dec
10,
--
F--I--|--
10 "
g'S10"
I
II
:1-di
:- A
--*-
C10
10-"
I
M
0
10'
100
-0.2
_OA
0
OA
"ae Volt
02
I
0.3
0.A
M
Figure 0-3 (Left) Simulated subthreshold characteristics of a nanowire FET with imaginary ideal
band structure at the source showing very steep swing. D is the nanowire diameter. Ns is the
source doping level, AEc is the extension of the conduction band (Figure taken from [5])
24
The potential of using a superlattice as the energy filter to realize steep turn-on characteristics in
nanowire MOSFETs has been examined through simulations by Gnani et al [6, 7, 26] and
showed promising results. The simulated structure was a nanowire FET with a superlattice
interposed between the source and channel regions (Figure 2-5). Several III-V semiconductor
pairs commonly used for HEMTs and lasers haven been investigated. The optimal well and
barrier thicknesses that ensure the best trade-off between switching slope and on-state current
are reproduced in Table 2-1, with the subthreshold characteristics in Figure 2-6. Nw is the
doping concentration in the well regions of the superlattice, D is the nanowire diameter and tax
is the effective-oxide-thickness (EOT). Among these material options, InGaAs/InAlAs lattice
matched to InP is capable to deliver an subthreshold swing of 13 mV/dec and an on-state
current of 4.5 mA/um, at VDD
0.4 V. The transfer characteristics of this material pair is shown
in Figure 2-6, demonstrating excellent pitch-off. From Table 2-1, we note that the layers of SL
need to be very thin.
a
A
b
AS
2d
>0
1
4
04-0
Oii
a
Ad
Ar
b
ASA.nlA
As.,w
Miibn A
was
Miniga
MMiniban
Figure 0-4. a. Superlattice formed by alternating GaAs/AlAs layers and the corresponding
potential energy profile (Figure taken from [2]). b. Allowed minibands (the shaded area)
calculated as a function of well or barrier width and the corresponding potential energy
profile (Figure taken from [2]). c. Schematic illustration of minibands and minigaps with
regard to the original conduction band structure.
25
drain
I
M
Iw
Vo $b
Figure 0-5. Schematic illustration of simulated nanowire FET and conduction band diagram
of superlattice (Figure taken from [7]).
Pair (A)
Materials
Pair (B)
GaN/Alo.15GaO.85N GaN/AlO. 25GaO. 75N
Pair (C)
Pair (D)
InGaAs/InAlAs
InGaAs/InP
w/nm
1.5945
1.5945
2.9335
2.9335
b/nm
0.9567
0.9567
1.1734
1.1734
Table 0-1. Well (w) and barrier (b) thickness for the four material pairs simulated. (Data
taken from [7]).
le-
10
V1,S=O.4V
le-03
6
/
6OV/ddc., -
Dln
1e-05
1e-07
C
18-09
C
le-1
le-13
1-15
Figure 0-6. Subthreshold characteristics normalized to diameter for different SL material
pairs. (Figure taken from [7]).
26
2.3 Quantum Mechanical Simulations of the Band
Structures of Nanowire Superlattice
A simulation environment which can capture the essential physics is necessary to help
understand various effects and maximize device performance. As superlattice normally features
layers with thickness of 1-10 nm, quantum effects are very prominent. To this effect, we have
explored a Poisson-Schrodinger solver called Nextnano, which can solve the Poisson equation
and Shrodinger equation self-consistently. In this section, the band structure of a superlattice
and the effect of transversal confinement were simulated using Nextnano.
2.3.1
Nextnano Simulation of the Band Structure of Superlattice
To verify the capability of this solver, we first simulated the band structure of a superlattice
along the growth direction and calibrated the results with literature values. The superlattice
simulated was GaAs/A1O. 3GaO. 7 As/..., which was assumed to be infinite in the growth direction
by having periodic boundary conditions, and have infinite transversal plane. So the transversal
direction is decoupled from the growth direction as there is no confinement in the transversal
direction and electrons will move freely. In the growth direction, however, minibands and
minigaps will form due to periodic potential from alternating layers of GaAs and AlGaAs. For
well thickness of 15 nm and barrier thickness of 2.5 nm, the simulated eigenstates and
eigenergies at kz=0 with respect to the conduction band profile in one period of the superlattice,
1.25 nm Alo. 3Gao. 7 As/15 nm GaAs/ 1.25 nm Alo.3Gao.7 As was shown in Figure 2-7.
If we plot eigenenergies against wave vector along the growth direction kz instead of position,
we will have the band structure which features minibands and minigaps, as shown in Figure 2-8.
Here L is the period of the superlattice, which is 17.5 nm.
To calibrate the simulator, we calculated the band parameters of three types of superlattice of
the same materials, but with different well thicknesses. The calculated parameters included the
energy position of the first miniband with respect to the conduction band edge A01, the width of
the first and second minibands,
AMB1
AMB2,
and the minigap between them A12. The barrier
thickness was 2.5 nm, the same for all three types. The results were listed in Table 2-2 in red,
27
Conduction band edge
Second elgenstate
First eigenstate
Second eigenenergy
First eigenenergy
N.
AIGaAs
C
GaAs
7z
> AIG aAs
Figure 0-7. Calculated first and second eigenstate/eigenenergy with respect to
the conduction band profile for GaAs/AlGaAs superlattice.
E/eV
A
0211
2"d miniband
023
1 St minigap
on
1st miniband
U0
of
02
03
02
05
-
0's
-
07
-
-
-
-
-
01
-
-
-
0s
I
io
kzl-
L
Figure 0-8. Calculated band structure for GaAs/AlGaAs superlattice, including
the 1s, 2 "dminiband and the minigap in between.
together with those obtained from reference [3] (in black) where the identical structures were
also simulated. It can be seen that good agreement was achieved, confirming the validity of our
simulator.
28
Parameters
Unit
Sample 1
Sample 2
Sample 3
Well
nm
6.5
8.5
15
A0_
AMR1
meV
46/47
33/34
14.5/14.9
meV
22/20
13/11
3.5/3.0
AB
meV
114/117
85/89
40/42
IA12
meV
94/90
53/49
14/13
Table 0-2. Comparison of calculated band parameters of three types of
AlGaAs/GaAs superlattices with a barrier thickness of 2.5 nm and various well
thicknesses between literature ([3], in black) and Nextnano simulations (in red)
The dependence of the band structures on the well and barrier thickness is worth discussing,
because the width of miniband and minigap will affect the subthreshold and on-state current of
superlattice-source FETs, which will be discussed in section 2.4.4. From Figure 2-3b we can
see that the miniband width increases with thinner well or barrier thickness. As stated in section
2.2.3, the miniband can be viewed as the broadening of single energy level within the well due
to the coupling of the energy levels in adjacent wells separated by barriers (this is similar to the
way of thinking about bands in crystals as the broadening of single atomic energy levels due to
the coupling of these levels in adjacent atoms). The miniband width is related to the strength of
the coupling between energy levels within adjacent wells. Decreasing the barrier or well
thickness increases this coupling and hence results in a wider miniband. The dependence of the
minigap width is more complicated, as it is determined by the separation of different energy
levels within the well subtracted by the extension of the miniband widths. When well thickness
drops, the separation of the different energy levels rises (the confinement length is reduced so
quantization gets stronger) but the extension of the minibands increases as well. As a result, the
minigap width first increases and then drops with thinner well thicknes, as can be seen from
Figure 2-3b.
2.3.2
The Effect of Transversal Confinement on the Band Structure of
Superlattice
In the previous section, the superlattice studied was assumed to have infinite transversal plane
perpendicular to the growth direction. Here we release this constraint and investigate the effect
29
of lateral confinement imposed by the finite dimension when the superlattice has a nanowire
cross section. The formation of sub-bands in thin nanowires has been studied both theoretically
and experimentally [30, 31]. Here we will show that in addition to minibands, subbands will
form in the nanowire superlattice.
Along the growth direction, the simulated superlattice was 2.94 nm Ino. 53Gao. 47As/ 1.18 nm
Ino. 52 Alo.4gAs/..., which was identical to pair (C) in Figure 2-6. In the direction perpendicular to
the growth direction, the electrons were confined in a square by assuming Dirichlet boundary
condition to its sides (which meant that the nanowire had a square cross section). Figure 2-9
shows the band structure along the growth direction when the side of the square was 7 nm.
Distinct features emerge here as compared to Figure 2-8. While in Figure 2-8 there were only
two minibands, lateral confinement in Figure 2-9 leads to the formation of subbands for each
miniband. For the same miniband but different subbands, the difference between them is the
different quantization energy in the confined direction (perpendicular to the growth direction).
Graphically, bands in the same miniband but different subbands have similar shape. For
example, in Figure 2-9, the second band which corresponds to 1st miniband and 2 "dsubband, has
similar shape to the first band.
E/eV
1 st
subband, 2nd miniband
Figure 0-9. Calculated band structure for 2.94 nm InGaAs/1.18 nm InAlAs
superlattice along the growth direction. In the perpendicular direction,
electrons are confined to a square with a side of 7 nm.
kz/-
L
E/eV
39
33
32
I
The energy difference is 0.12 eV
29
28
1 subband, 1 s' miniband
27
26s .
01
0
03
o2
0s
o4
0s
or
00
o1
r
kzl/L
Figure 0-10. Zoom-in of figure 2-9 showing the first three subbands more clearly.
The energy separation between the first and second subband is 120 meV.
5z
0.25-
U)
0.200.15-
0.100.050.00
-0.05 -0.10
-0.15
I
5
I
6
7
8
9
10
11
12
13
14
Length (nm)
Figure 0-11. The energy separation between the first and second band versus
nanowire cross-sectiony dimension for otherwise the same superlattice in Figure
2-9 and 2-10.
31
As the nanowire dimension is reduced, the energy separation of different subbands increases.
We are interested in the critical dimension where the energy separation is large enough such that
there is no overlap between the 1 st and
2 nd
subband and essentially we can have single subband
conduction. Figure 2-10 depicted the 1st and
2 nd
subband at a better energy resolution and we
can see that the energy separation between these two bands is 0.12 eV. The positive sign here
means that the highest energy in the first subband is lower than the lowest energy in the second
band. To have a better understanding of the critical dimension for single subband conduction,
the energy separation between the first and second band was plotted against the length of the
side for the nanowire cross section in Figure 2-11. In the case of Figure 2-10 where the
nanowire diameter is around 7 nm, the energy separation will be as large as 0.12 eV, which is
equal to 5kT, with T=300K. In order to have single subband conduction, a technology is needed
to fabricate nanowires with physical cross-sectional dimension below 10 nm.
2.4 Device Design Issues
Following calculation of idealized band structure, important device design issues such as
possible device architectures, superlattice doping, material systems and non-idealities will be
discussed in this section.
2.4.1
Possible Device Architectures
As stated in section 1.3, a nanowire design and a wrap-around-gate are essential elements of the
SLS nanowire FET device architecture. Except for the benefit of single subband conduction and
strong gate control, volume inversion effect is another result of electron confinement due to the
nanowire configuration. Normally, in nanowires fabricated by top-down approach, it is expected
that reducing the nanowire size will degrade transport due to the relative increase in surface
roughness scattering given the larger surface-to-volume ratio. However, it has been reported in
top-down InGaAs nanowire that the transport properties could be improved as evidenced by the
estimated 20% increase in mobility when the nanowire is reduced from 50 nm to 30 nm [8]. The
reason behind this improvement is that the stronger quantum confinement at smaller wire
dimensions which will push the inversion layer further away from the surface. As a result the
32
transport will be less affected by surface roughness scattering. In the TCAD simulation shown
in Figure 2-12 [8], the inversion layer in 30 nm wire is pushed 1-2 nm further away from the
surface. The effect is more pronounced in InGaAs than Si because of the smaller effective mass
in InGaAs.
In this study, a vertical transistor architecture is proposed, and schematically drawn in Figure 213. As will be discussed in section 2.4.5, a high quality superlattice region which has sharp
transition between different materials is necessary to obtain a steep turn-on. To this regard,
MBE growth of the superlattice is preferred due to its monolayer accuracy. Since the MBE
growth direction of the superlattice is inherently vertical, the current flow has to be vertical as
well. This design features a top-down etched nanowire, an ALD gate oxide and wrap-aroundgate, and a superlattice source region.
(a) Unit:-.
Electron DesIty(e
3
)
(b)
S1
30
.nu
IGoos
nA
1Ox i0rtM
2.0E+16
20
9.7E+16
s1 1OXionm.O
n
E
2.3E+18
10
1.1E+19
0~
SIF
9
1019
w
S 30X3
nGaAs 3OX30n
10"8
30\
20,
1
nGaAs OX30nm
X30nm
10
0.0 0.2 0.4 0.6 0.8 1.0
*
10
i*
3
Normalized Width
Figure 0-12. a. Cross-sectional distribution of electron density in the InGaAs nanowire
with side length of 30 nm and 50 nm at VGs-VT= 1.2 V. b. Normalized electron distribution
at the middle of the nanowire for square-shape Si and InGaAs nanowires. (Figure taken
from [8])
33
Figure 0-13. Diagram of the proposed superlattice source nanowire FET.
2.4.2
Number of Periods of Superlattices
Comparing Figure 2-3 to Figure 2-6, the subthreshold swing increased from 3 mV/dec to a few
tens of mV/dec. The reason is because in Figure 2-3 a perfect band edge of an imaginary band
was assumed, while in Figure 2-6, an actual superlattice acted as the energy filter and the band
edge cannot be ideal. To understand the effect of band edge more carefully, let's examine
closely what will happen when the device is in the subthreshold with the help of Figure 2-14.
Figure 2-2b was reproduced here as Figure 2-14a.
34
b
Band edge
Figure 0-14. Conduction band diagram when device is biased in the subthreshold
regime a. The imaginary minibands that have infinitely sharp band edge. b. Real
minibands formed by a superlattice with finitely sharp band edge.
In the case of Figure 2-14a, the imaginary band structure assumed a perfect band edge. This
means that, there were no states available in the minigap, and as soon as the energy was in the
miniband, the density of states available increased infinitely fast. In this case, the subthrehsold
current is contributed by direct source to drain tunneling. However, in the case of Figure 2-14b
where superlattice was used as the energy filter, the band edge was not perfect due to the fact
that there is a finite number of periodsin the superlattice. In this case, as we show below, the
available states extend into the minigap. At first glance it seems that the subthreshold swing
would still suffer from 60 mV/dec limit as equation (2.1)-(2.4) suggested, however, there is one
critical difference. Following equation (2.4), the subthreshold current is still proportional to:
ntaa = feOs g(E)f(E)dE
(2.4)
Instead of a g(E) oc \5 as is in the case of a normal MOSFET, now we have an exponentially
decaying g(E), as evidenced below in Figure 2-15b. So the Fermi-Dirac function f(E) is no
longer the single dominant factor, since g(E) is also exponential. Hence subthreshold swing S
can be expressed as:
35
dlog1 f f(E)dE
dlog1 0 f g(E)dE
do#s
(1 11
60
Here fl =
dops
60 x fl mV
(2.6)
60 + fl dec
dE
d(log 1 o f g(E)dE)
We can see that fl is a measure of the rate at which the density of state decays when energy
increases at the band edge. This equation also emphasizes the concept of density of states
engineering by the assertion of the superlattice acting as the energy filer.
To verify that the density of states actually has an exponential tail, the ballistic transmission
probability was calculated through the unbiased superlattice region, using the Contact Block
Reduction method implemented in Nextnano. The superlattice simulated was 2.94 nm
Ino. 53Gao. 47As/ 1.18 nm lno.52Al 0.4sAs/..., which was identical to pair (C) in Figure 2-6, and had
an infinite transversal plane. The conduction band profile is shown in Figure 2-15a, for a
superlattice with 10 periods. The simulated transmission probability is plotted in a logarithmic
scale against energy, for both 7 and 10 periods of the same superlattice, in Figure 2-15b. From
this figure it is clear that there is a finite density of states available in the minigap, and at the
band edge the transmission probability T decays exponentially. Also worth noting is that, T for
10 periods is sharper than that for 7 periods, which suggests a smaller
f#for
the 10 period
superlattice, and hence a steeper S. The average S of a nanowire FET incorporating this
superlattice was 23 mV/dec, as calculated by Gnani et al [7]. We can also estimate the S based
on the picture we just developed. As seen from Figure 2-15b, for 10 periods, T decreased from
1 to 7.6 x 10-6 as the energy increased from 2.67 eV to 2.87 eV, which gives an average # of
39 mV/dec. Plug this number into equation (2.4) and note that n = 1 in their simulated structure,
39 x 60
S = 1 x 3 + 60 = 24 mV/dec
39 +60
The good agreement suggests that the transistor is actually limited by the energy filtering
capability of the superlattice region.
36
However, there is a trade-off in terms of the drive current when a large number of periods is
used. When the barrier number increases, the total transmission within the miniban decreases,
and therefore the drive current is reduced. In Figure 2-15b, it seems that the total transmission is
fairly constant for 7 and 10 periods. The reason is because in this simulation, the transport was
assumed to be ballistic, and the peak transmission in the miniband is always 1 no matter how
many periods there are. In a real device where scattering is presented, the peak transmission will
be less than 1 [32]. In this case, the more periods we have, the less the peak transmission will be.
As a consequence the drive current will decrease. In the simulation performed by Gnani et al,
this reduced drive current cannot be predicted, as their transport model is ballistic as well. In
Figure 2-16 [6], the drive current is seen to be the same for different number of periods of the
superlattice. The subthreshold swing starts to degrade when the number of periods is less than 8.
2.4.3
Superlattice Doping
The necessity of heavy doping in the superlattice region is best explained by Figure 2-17 [4]. In
this simulation, nanowire FET has a diameter of 5 nm, an EOT of 1 nm, and a source/drain
doping level of 2 x 1020cm- 3 . Comparing (a) and (b) in Figure 2-16 (left), device (a) suffers
from poor subthreshold slope and degraded on-state current. This difference is caused by the
capacitive coupling of the superlattice with the gate which heavily affects the electrostatic
potential in the SL region, as seen by the corresponding conduction band profile (top right).
Since the SL region is undoped, the voltage difference between the source and gate is partially
absorbed by the superlattice, and therefore the miniband potential increases with the channel
potential. As a result, the energy filtering capability of the superlattice is compromised. Direct
source/drain tunneling could explain the improved performance from device (b) to (c) as a result
of the increase in gate length.
In addition to suppressing the capacitive coupling between gate and the superlattice region,
doping in the SL region also affects ION, IOFF and the on/off ratio. When the doping
concentration is higher in the SL region, the Fermi level will come closer to the 2
miniband.
The off state leakage current contributed by the thermionic emission from higher minibands will
then increase. When the channel potential is at the same position relative to the conduction band
37
a
E/eV
I77-
Z/Rm
b
o Band edge
1--.0
01
-
e
0.01
I1E-3
a
1E-4
1E-5
.
10 Penods
7 Peiods
1EE6
2.4
2.5
2.6
2.7
2.8
29
3.0
3.1
3.2
E (eV)
1st miniband
1st minigap
2 nd
miniband
Figure 0-15. a. Conduction band diagram for the 10 periods of InGaAs/InAlAs
superlattice simulated. a. Ballistic transmission probability calculated for 7 and
10 periods of superlattice.
edge of the superlattice region at on state, the drive current will be larger in devices with higher
doping since there will be more electrons that can travel across the barrier. To quantify the
trade-off in the on/off ratio, we referred to the simulation performed in reference [6], as
reproduced here in Figure 2-18. The device geometry was the same with that in Figure 2-16.
Label (A)-(F) indicated the SL region doping level ranging from 2 to 9 x 1019 cm- 3 , with a
step of 1019 cm~ 3 . From the top right figure we can see that the average subthreshold swing
was almost independent of the doping level. The trade-off between off state leakage current and
on state current can be seen from the bottom left figure. For IOFF below 10-10 A/um, 2 x
38
1019 cm- 3 doping level can provide the highest drive current. For IOFF value larger than
108 A/um, a doping level of 9 x 1019 cm~3 can give the highest drive current. For IOFF values
in between, other doping level gave the best trade-off. The general trend was that, for larger off
state current higher doping level provided the highest drive current. This means that for
different applications different well doing concentrations should be used.
1e-03
Voa= 0.1 V
NY =3x109 cm-3
E
E
1e-05
SS [m/dec]
&Nomapeak
0)
average
-num.
1e-07
b=10
19.5
31.1
Z3-
num. b=9
21
31.6
C+-
num. b=8
23
33.8
-* num. b=7
26
39.1
T-V num. b=5
35
46.2
11e-09
le-Il1
-0.1
0
0.1
0.2
0.3
0.4
Gate voltage [V]
Figure 0-16. Simulated transfer characteristics for different periods of
superlattice. Wire diameter D= 5nm, EOT= 1nm. Superlattice is comprised of
1.59 nm GaN/ 0.95 nm AlGaN (Figure taken from [6])
2.4.4
Material System
The choice of material system is clearly of central importance for the demonstration of this
device concept. Due to the ability of growing high quality heterostructures and various types of
band alignment available, the III-V material system is naturally suited for this purpose. Actually
III-V superlattices have been explored extensively in the field of quantum cascade lasers (QCLs)
39
[33]. Also, motivated by the high electron mobility in III-V materials, recently III-V CMOS
technology has raised great interest as an extension to Si CMOS technology and tremendous
progress has been made [9]. Engineering DOS at the source could further improve the
performance of III-V MOSFET.
There are a number of III-V material pairs that are commonly used in HEMTs and lasers, such
as InGaAs/InAlAs, GaAs/AlGaAs, InAs/GaSb and GaN/AlGaN, etc. To evaluate the potential
of these materials for the operation of SLS-FET, optimum device performance based on these
pairs have to be simulated. This involves the optimization of various device parameters such as
barrier and well thicknesses for the superlattice, superlattice doping concentration, channel
length, etc, for each of these pairs. Figure 2-6 represents such a simulation performed by Gnani
1
10
0.5
0
-0.5
1
10-
0.5
5'
0
o 1012
C
-0.5 W
W~
I
0.5
0
10~1
10~i
-O LG=10 nm, SL undoped
"- L=10 nm, N,=10 9 cm 3
A-A LG=20 nm, N=1019 cm 3
-0.2
0
0.2
5-0.5
0.40
Gate voltage [V]M
10
20
30
40
50
Position [nmJ
Figure 0-17. (Left) Simulated transfer characteristics for SLS nanowire FETs
with different gate lengths and doping levels in the SL region. The values were
labeled in the figure. (Right) Conduction band profile of the simulated devices
for various gate voltages (Figure taken from [4])
40
1e+0s
60
E peak
U
A-A (C)
le+06
average
4-4 (D)
40"G
(E)
It0
+-+ (F)
Sle.04
50
30E
co)
20
1.+02
0.8
10
0.2
E
0.4
0,2
18-11
0.1 >
V =0.1 V
le-09
1e-07
10FF
['Ajpm
le-05
(A) (B) (C) (D) (E) (F)
0
Figure 0-18. (Left) On/off current ratio (top) and ION (bottom) vs. IOFF- ION was calculated
at VDS=O. 1 V and VGS=0.4 V. (Right) Peak and average S (top) and gate voltage ranges
over which the peak and average S are stable (bottom). From (A) to (F), doping level
increases from 2 to 1019 cm-3 , with a step of 1019 cm-3 . (Figure taken from [6]).
et al, where four different material pairs were simulated. In this idealized simulation, the
fundamental differences between different material pairs were the effective masses and the
conduction band offset. Compared to InP material system (pair (C) and (D)), GaN material
system (pair (A) and (B)) has much larger effective masses. So the optimum barrier and well
thicknesses for the superlattice will be smaller to ensure enough extension of the miniband and
minigap. Still, the optimized miniband extension is still smaller, and therefore the drive current
will be smaller in GaN material system. Moreover, the smaller barrier and well thicknesses are
more challenging in terms of growth. InGaAs/InAlAs heterostructure has a conduction band
offset of 0.5 eV, while only 0.22 eV is present for InAlAs/InP heterojunction. A large
41
conduction band offset guarantees enough minigap, which results in smaller leakage current and
steeper subthreshold slope. Practically our group at MIT has rich experience with
InGaAs/InAlAs lattice matched to InP, hence our device will be demonstrated in this material
system.
2.4.5
Non-idealities in the Subthreshold Regime
Until this point the discussions and the simulation work referenced have been rather ideal.
Experimentally non-idealities often dominate and mask the desired intrinsic properties.
Although it's too early to have an in-depth study of the various non-idealities, an effort to
recognize some of them and discuss the possible consequences is still necessary.
Equation (2.6) included the effect of non-ideal band edges in the expression of subthreshold
swing. It pointed out that the sharper the band edge is, the steeper the turrn-on will be. The
relatively soft band edges in Figure 2-15 is a consequence of the finite number of periods of the
superlattice. In practical devices, the tail at the band edges will be caused by any imperfections
in the lattice, such as phonons, doping, etc. All these imperfections will increase fl and leave us
with a larger S. Phonons can definitely induce band edge states. In silicon, the optical
adsorption coefficient falls off as an exponential at the rate of 27 mV/dec [34]. This coefficient
is proportional to the joint density of states between conduction and valence band, and therefore
the exponential fall-off suggests that the density of states should follow the same pattern. Heavy
doping is another source of large density of states at the band edge, as dopant atoms disturb the
idea lattice structure. Recently Sapan et al [35] extracted a minimum conductance slope of 120
meV/dec in a diode doped to near 10
20
cm- when it was biased as a backward diode. This
slope was limited by the band edges, hence implying the existence of a tail in the density of
states decaying in a similar fashion. This is one reason that the doping concentration in the
superlattice region cannot be too high. For superlattices, in addition to the requirement of a high
quality crystal structure for each of the constitutional material, the interface between the
material pairs has to be as sharp as possible, which necessitates MBE growth.
Another important issue is to find a suitable gate dielectric to the III-V material. Compared to
the gifted interface between Si/SiO 2 , the interface between III-V compounds and the native
42
oxide suffers from larger imperfections such as much higher trap density, which usually results
in "Fermi-level pining". Recently, high-k dielectrics such as A12 0 3 and HfO2 deposited by
atomic layer deposition (ALD) have been shown to yield a better interface to III-V materials [9],
but substantial interface trap density Dit is still present which will result in an n in equation (2.6)
significantly larger than 1. Di, between ALD A12 0 3 and Ino. 53 Gao. 47As can be reduced down to
2 x 101 2 cm~ 2 eV-1 [36]. However, for InGaAs MOSFET, the best result so far has been
obtained on a buried channel structures equipped with an InP barrier layer using ALD TiSiOx as
the gate dielectric [37]. In our device architecture, the InGaAs surface will be exposed by dry
etchibng and an InP capping layer cannot be present unless a regrowth is done.
2.5 Summary
The central device concept of the superlattice source FET (SLS-FET) was introduced in this
chapter. Our own quantum simulations of the superlattice were presented and the critical wire
dimension for single band conduction was computed. Several device design issues were
discussed and possible trade-offs for various device parameter were pointed out. In the next
Chapter, we will move on to talk about the overall process design and various process
technology modules that have been developed.
43
44
Chapter 3 Technology for SLS nanowire FETs
3.1 Introduction
As discussed in section 2.4.1, a vertical transistor architecture will be pursued in this study. The
material system contains InGaAs and InAlAs lattice matched to InP, with different doping
concentrations. To realize single subband conduction, a process technology that can fabricate
sub-10 nm diameter III-V nanowires is necessary. In this chapter, the overall process design will
be presented and key fabrication technologies will be discussed in detail.
3.2 Overall Process Design
Major steps of SLS nanowire FETs fabrication are shown in the process flow in Figure 3-1. The
starting substrate will be semi-insulating InP. The heterostructure will have InGaAs as the
source, drain and channel region, while the superlattice region features alternating layers of
InGaAs and InAlAs that will be inserted between the source and channel. All materials are
lattice matched to InP.
HSQ, a negative-tone resist is first exposed via electron beam lithography (EBL) in a dot-shape
and serves as the hard mask for subsequent pillar dry etch. A nano-pillar is then formed by
reactive ion etching (RIE) where the unmasked semiconductor is etched away. As there is no
etch stop for the selected chemistry, the etching depth is controlled by timing the process. A
digital etch is performed to further thin down the nanowire and partially remove the dry etch
damage during the RIE process.
In order to achieve a uniform coverage of gate dielectric and gate metal, ALD high-k/metal gate
is chosen due to the excellent conformality as well as the scalability for thin effective-oxidethickness (EOT). The high-k dielectric will be A12 0 3/HfO2 , and WN will be deposited as the
gate metal. Since the gate metal is now covering
45
Side View
Top View
InGaAs
Superlattice
Adhesion
layer
Starting
substrate
HSQ
ALD-A120 3
Step 1
Mask definition
ALD-WN
by EBL
SOG
Contact metal
Step 2
RIE and cleaning
Step 3
Digital Etch
Step 4
High-K/Gate
metal deposition
and patterning
Gate
Step 5
Planarization and
etch back
Step 6
Planarization, etch
back and G/D
contact opened
Step 7
Metalization
Figure 0-1. Process flow of SLS nanowire FETs
46
the whole wafer surface as a result of the ALD process, a photolithography step using negative
resist is needed to remove the unwanted WN. In order to control the gate length, spin-on glass
(SOG) is deposited and etched back afterwards in the CF 4/H2 chemistry which will attack WN
at the same time. Note that the etch back process has to be timed accurately so that the SOG
surface can stop at the interface between the superlattice and the channel region, to minimize
the capacitive coupling between superlattice region and the gate, as illustrated in the step 5 in
Figure 3-1. The substrate will be immersed in NH 40H/H20 2/H 20 solution (which doesn't attack
SOG and gate dielectric) to remove any WN residue to avoid the potential shorting between
gate and drain. Another planarization and etch back step is adopted to form the isolation
between gate and drain metal. Again, the SOG surface will stop at the interface between InGaAs
source/superlattice region by timing. The source/drain ohmic contact and gate metal pad will be
formed via lift-off at the end.
In this process flow, critical fabrication steps are EBL, RIE, digital etch, planarization and gate
technology which includes ALD high-k/gate metal and relevant etching. Except for the gate
technology, other four steps have been developed and will be discussed in detail below.
Development of the gate technology has been delayed due to equipment isses in the lab.
Nevertheless, etching properties of the gate metal WN and ALD dielectric A12 0 3 are being
studied on silicon wafers.
In the following section, the heterostructure that was used is shown in Figure 3-2 unless
specified. The sample was grown by metal organic chemical vapor deposition (MOCVD) at
MIT. All the materials were lattice matched to InP. Note that this heterostructure was not the
final design. It was chosen for the purpose of process development because it is made in the
material system that we want to work with, and was immediately available at hand.
3.3 Process Technology
3.3.1 Electron Beam Lithography
From the discussion in Chapter 2 we know that a pillar with a sub-10 nm diameter is needed in
order to obtain single band conduction. With the help of digital etch which will be discussed in
47
section 3.3.2, the hard mask has to be defined with a resolution of sub-20 nm. In order to define
isolated dot-shape mask with such a resolution, electron beam lithography (EBL) and a
negative-tone resist have to be utilized. EBL in this work was first performed in a Raith
1 5 0 Tm
system and later in an Elionix ELS-F 125 system for better result and yield. In any lithography
process, the first step is to select a resist and identify the appropriate dose for pattern definition.
Hydrogen Silsequioxane (HSQ) was chosen because it is a negative-tone resist and can achieve
sub-10 nm resolution [38]. It can serve as the etch mask itself for III-V semiconductor RIE and
eliminate the need for additional hard mask, since it resembles Si0 2 , especially after annealing.
HSQ is a spin-on dielectric with the chemical formula of (HSiO 3/2)n, where n is the number of
monomers with a typical value of n=8, forming a cage-like structure [39]. Upon exposure, high
energy electron beam breaks the Si-H bonds and reconfigures the cage-like structure to a longrange network via a cross-linking process [40]. HSQ used in this work was a flowable oxide
(FOx) diluted with Methyl-IsoButyl-Ketone (MIBK), available under trade name of XR- 1541M
(from Dow-Corning*). The development mechanism of HSQ is suggested to occur via
ionization by bond-decision, rather than dissolution [39]. Hydroxide (OH-) ions in the developer
such as Tetra-Methyl-Ammonium Hydroxide (TMAH) can break the Si-H bonds, lead to
stronger Si-O bonds and can be carried away by the (CH 3)N' ions and water molecules [41].
15nm
2 nm
50 nm
500 nm
500 nm
Figure 0-2. The heterostructure used in this work. All layers are lattice matched to InP.
A typical process for HSQ exposure used in this work is summarized in Table 3-1. HSQ is
believed to suffer from adhesion problem when deposited on a variety of materials, including
metal and compound semiconductors [42]. It is well known that HSQ exhibits good adhesion on
Si [43], so a thin layer of Si was evaporated to improve the adhesion to InGaAs in this study.
48
Figure 3-3 showed the HSQ lines defined on the heterostructure shown in Figure 3-2, following
the same process flow. The only difference is that a 3 nm Si layer was evaporated onto the
substrate in Figure 3-3b. The line width was 40nm, 70nm, 100nm and 600nm, respectively.
While the substrate with the adhesion layer resolved the lines very well, the same structures
directly on the InGaAs sample were collapsed, and the 40 nm line was not even there. The
adhesion layer cannot be very thick as the pattern has to be transferred to this adhesion layer
through RIE and a thick layer will degrade the resolution, which is critical in this study. Si layer
has the additional benefit that it will be etched by the Cl 2 chemistry used in this study and won't
be too resistive to the etching. Also, adhesion is a surface mechanism so that the adhesion layer
does not need to be thick as long as long as the surface can be covered.
HSQ is available with different solid concentrations from 1% to 6%. The higher the solid
concentration, the thicker resist one gets for the same spin speed. The proper resist thickness
would be around 50 nm in this work, which was determined by the trade-off between the
resolution needed and the mask erosion during the subsequent RIE. In order to reach a
resolution of sub-20 nm, the resist cannot be too thick to maintain an acceptable aspect ratio, or
the HSQ pillar after development will fall down. If the resist is too thin, it cannot survive the
RIE afterwards. As will be discussed in the next section, the resist thickness should be thicker
than 30 nm to survive the RIE process. If the resist was as thick as 90 nm, for a 20 nm
resolution the resist was not mechanically strong enough to stand up, as evidenced in Figure 3-3.
A suitable thickness would be around 50 nm. In Table 3-2, the thickness ranges of different
solid concentrations of HSQ are shown. From this table in order to have a resist thickness of
around 50 nm, 4% HSQ with a spin speed 4000 rpm was chosen. 2% HSQ with a spin speed
around 1000 rpm can also offer the desired thickness, but the spin speed was at the low end,
only around 1000 rpm. Therefore 4000 rpm of 4% HSQ was preferred as a higher spin speed
can lead to better uniformity. Unless specified, in this Chapter the HSQ thickness was about 50
nm.
49
a
b
Figure 0-3. Top view SEM images of the HSQ line structures defined following the same
process flow, except that a Si adhesion layer was evaporated onto the substrate in (b).
Process Step
Process Details
Storage
Refrigerate XR1541 4% in a plastic container, at 5'C. (Glass container
cannot be used)
Adhesion promoter
Resist spin
Evaporation of 3nm silicon layer via TRL-eBeamAu as the adhesion layer
Let the resist sit in the room temperature for half an hour to bring the
resist to room temperature. Drop the resist by Polypropylene pipettes to
cover the entire piece, spin at 4000 rpm for 1 min using TRL-Spinner
Exposure
Immediately after spin, using Elionix ELS-F125 system to expose the
resist. Parameters used: electron acceleration voltage: 125 keV, field size:
150 pm, beam diameter: around 1.7 nm, step size: 0.625 nm, beam
current: 200 pA, dose time: 0.2~0.4 ps (depends on the pattern size, as
will be discussed below.)
Development
Usually immediately after the exposure, in 25% TMAH for 120 s,
spin/rinse/dry
Table 0-1. Optimized process flow for EBL using HSQ resist
50
Solid concentrations for HSQ
Thickness range for typical spin speed (1000~5000 rpm)
1%
14 ~ 28 nm
2%
30~-45nm
4%
45
6%
85 -190nm
90 nm
Table 0-2. Thickness range of HSQ with different solid concentration, at typical spin speed
Note that right after the spin, unlike common resist process, no prebake is performed for HSQ
due to consideration of the resist contrast. Resist contrast is a measure of how well the resist can
convert the distorted patterns of a blurred aerial image into a sharp binary stencil, and directly
affects the resolution of the entire lithography process. Similar to what will happen during the
electron beam exposure, thermal processing such as baking at an elevated temperature will
cause Si-H bond excision and recombination will occur simultaneously favoring the transition
to a network structure reducing the cage/network ratio [44]. The major different is that the
energy deposition in the case of electron beam exposure is higher than that of thermal
treatments. Bond excision and network formation should therefore be, more pronounced than
during the baking. Baking can therefore be considered as a kind of pre-exposure of the entire
HSQ resist film, and hence the contrast will be decreased [44]. For similar reasons, HSQ is
usually exposed right after the spin, and developed right after the exposure. Exposure of HSQ to
oxygen in the atmosphere will tend to promote the excision of Si-H bonds as well as the
network formation.
Development and dose play important roles in determining the resist resolution and sidewall
profile. TMAH with concentration of 2.38% and 25% are commonly used for photoresist
development. 25% TMAH is reported to have better reproducibility and contrast for HSQ, and a
development time of 1 min is commonly used [44]. Salty developer is shown to have even
better contrast than 25% TMAH and can be used to resolve dense features with sub-10 nm pitch
[45]. In this study, 25% TMAH rather than salty developer was chosen because the drawn
feature was isolated. 2 min development was performed to avoid an underdevelopment situation.
51
Before dose information was provided, it should be noted that Elionix ELS-F 125 system uses
dose time as a measure of the dose (which is the dwell time at each position that the electron
beam will be unblanked and exposure will happen, in the unit of ps/dot) instead of more
commonly used area dose with the unit of pC/cm2 . So the dose information below was recorded
in the form of dose time. In a dose test, different doses were assigned to dots with different sizes
in the Elionix pattern file (the drawn size), and all other parameters were the same with the
values shown in Table 3-1. For the same drawn dot size, the higher the dose, the bigger the
actual dot will be due to the proximity effect. In the 150 titled SEM image with regard to the
cross section shown in Figure 3-4, the drawn dot diameter was 30 nm in both cases, but the dose
time increased from 0.38 is/dot (on the right) to 0.6 ps/dot (on the left). Accordingly, the
actually dot diameter increased as well. Also, the sidewall was more vertical on the right, due to
less proximity effect. Proximity effect in electron beam lithography is caused by electron
scattering, including forward scattering caused by the resist, and back scattering from the
substrate. When the drawn size is larger, more electrons will pass through a fixed volume by
scattering from adjacent area, and thus the effective dose is larger. The dose required for the
actual pattern size to be equal to the drawn size increases when the drawn size is reduced (this
dose is referred to "the right dose" hereafter). Table 3-3 summarized the right doses needed for
different drawn dot sizes. In this study, the smallest HSQ dot obtained reproducibly was 15nm
in diameter, as shown in Figure 3-5. For a better resolution, thinner resist, smaller beam current,
and a smaller step size have to be used. Another interesting observation is illustrated in Figure
3-6. Even at the right dose, patterns with larger size suffered from more sloped sidewall, which
was another consequence of increased proximity effect.
5 nm
30 nm
M
Figure 0-4. 150 tilted SEM image of the dot pattern with a drawn diameter for 30 nm. The
dose time was 0.6 and 0.38 for the left and right figure, respectively
The drawn dot diameter (nm)
The right does time (ps/dot)
15
0.40
20
0.34
30
0.30
70
0.26
200
0.22
600
0.20
Table 0-3. The right doses for different drawn dot sizes
Figure 0-5. 150 tilted SEM image of the dot pattern with a drawn diameter of 15 nm.
600 nm
30 nm
Figure 0-6. 150 tilted SEM image of the dot pattern with drawn diameters of 30nm and 600
nm. The sidewall profile for 600 nm was more sloped.
As stated at the beginning of this section, Raith
15 0 TM
system was initially utilized for the
exposure, and later we switched to the more advanced Elionix ELS-F125 system. There were
several reasons for this change. Elionix system allows for a faster writing speed because a larger
current is available. The highest electron acceleration voltage available for Raith system is
53
30keV, while that for Elionix is fixed at 125keV. A higher acceleration voltage reduces the
forward scattering, and hence a smaller proximity effect can be anticipated. The major issue
with the Raith system for our purpose was the difficulty of obtaining a circular dot pattern. As
shown in Figure 3-7, top view SEM images of the dot pattern exposed by Elionix (left) and
Raith system (right) were compared. It can be seen clearly that the pattern exposed by Raith
turned out to be an elipse despite the fact that it was designed to be circular in the Raith pattern
file. The problem gets worse with reduced dimensions. The x-y rastering of the electron beam
during Raith system exposure the origin of this problem.
in
115nm
70
r
80nm
Figure 0-7. Top view SEM image of the dot pattern exposed with Elionix (left) and with
Raith (right), following the process flow shown in Table 3-1
A 30 minute 02 plasma anneal was usually performed to harden the HSQ prior to its use as an
etch mask in the subsequent dry etch that was used to define the semiconductor pillars. As can
be seen from next section, this treatment improves the etch selectivity considerably. The recipe
used for this anneal is summarized in Table 3-4.
Process Step
HSQ 02 plasma anneal
Machine
Asher-TRL
Process Details
400W, 30 minutes
Table 0-4. Process flow for 02 plasma anneal to harden the HSQ as the etch mask
54
3.3.2
Reactive Ion Etching
After the definition of the HSQ mask via EBL, the pattern was transferred to the substrate by
reactive ion etching. A conventional reactive ion etcher consists of a chamber with two parallel
electrodes. The sample to be etched is placed on one electrode and the other electrode is
grounded. A radio frequency (RF) voltage is capacitively coupled to the non-grounded
electrode, ionizing the gas molecules and creating a plasma. The radicals and ions of the plasma
chemically etch the sample. A pressure is maintained in the chamber by various valves. An
equilibrium DC bias voltage is created between the positive ions in the plasma and the negative
electrode. The DC bias causes the positive ions to accelerate toward the sample. This has a
major impact on the etching anisotropy. Reactive ion etching is the combination of chemical
etching by the reactive species in the plasma and ion bombardment, which not only enhances
the chemical etching, but also sputters away material. In a RIE etcher, the power fed to the
plasma and hence the ion density, can be controlled independently with regard to the DC bias,
which is a major advantage over traditional plasma etcher where the ion density and DC bias are
coupled.
Cl 2 based chemistry is commonly used for III-V (GaAs based material, InP based material, GaN
based material, etc) RIE for photonic, HEMT and HBT applications [46, 47]. Group III and
Group V elements are removed by forming volatile Chlorine contained compounds and/or
physical bombardment. It should be noted that Indium containing compound semiconductors
present difficulties in trying to obtain efficient and equal-rate removal of the Group V lattice
elements and the Indium element because In(Cl)x is non-volatile at room temperature, while
Group V and Cl compounds are usually much more volatile[47]. In this case, an elevated
temperature above 200 0 C is often used to balance the removal rate. In this study, Cl 2 gas was
employed as it can provide Chlorine contained reactive species for chemical etch[48]. Also, we
added BCl3 gas because it is reported to provide heavy positive ions such as [B(Cl) 2]+ to
improve the physical bombardment component in the etching and also offer reactive species for
chemical etch [49]. Physical bombardment results in improved anisotropy but often lowers the
etch selectivity to the mask. N2 has been reported to enhance the anisotropy by a possible
55
passivation mechanism of the sidewall and also reduces the sidewall roughness, however, the
physical mechanism is still subject to controversy [50].
For our device concept to work out, the RIE process has to fulfill the following requirements: a
vertical sidewall, an etching depth above 200 nm, and a smooth sidewall surface. This implies
an acceptable etch selectivity to the HSQ mask to guarantee tolerable mask erosion, good
anisotropy, no selectivity between InGaAs and InAlAs, and small sidewall roughness. There are
a number of parameters of the etch process to be optimized in order to get the desired etching
properties: gas flow rates, RF power, DC bias power, chamber pressure, temperature, and
etching time. For a selected etching chemistry, a parametric study has to be carried out and the
process is usually optimized iteratively for best etching results.
This etch was performed in the SAMCO Model 200iP Inductively-coupled Plasma (ICP) RIE
system. The optimized etch parameters for heterostructures shown in Figure 3-2 are
summarized in Table 3-5. Figure 3-8 shows SEM images of semiconductor pillars with different
dimensions after a 2 minute etch. The drawn HSQ mask size is (from the left to the right) 20 nm,
40 nm and 200 nm, respectively. It can be seem from the middle pillar image that HSQ mask is
still present, but the thickness was reduced from 50 nm to 20nm, resulting in a etch selectivity
of 6. Prior to the RIE, an 02 plasma treatment was not applied. The etch selectivity is increased
to 9 if the HSQ is hardened by a plasma. A 30 second buffered oxide etch (BOE) dip can be
used to remove the HSQ.
Parameter
Value
Gas
C12 /BCl 3 /N 2
Flow Rate (sccm)
Pressure (Pa)
ICP Power (W)
Bias Power (W)
Temperature (0C)
Etch Rate (nm/min)
Etch Selectivity to HSQ Mask
0/4.5/15
0.2
20
160
220
90
6~9 (after 02 plasma treatment)
Table 0-5. Optimized SAMCO ICP RIE parameters
56
From these images, a number of observations can be made. First, the sidewall profile was
almost vertical, signaling good anisotropy. Second, the sidewall roughness was below the
detection limit of the SEM, as evidenced by the 23 nm pillar in this figure. Third, a smooth
surface (the unmasked region) was also maintained after the etching. Forth, a resolution down to
20 nm can be obtained by the optimized etching parameters.
Fifth, although the etched
semiconductor contained InGaAs, InAlAs and InP, judging by the etching depth, the etch
profile was not material dependent. In the final heterostructure which contains InGaAs and
InAlAs, the etching profile will not change, but the etch rate needs calibration.
HSQri
210 nm
23 nim
180 nm
180 nm
Figure 0-8. 150 tilted SEM images of semiconductor pillars with different sizes after a 2
minute etch following parameters given in Table 3-5. The drawn HSQ mask size was 20 nm,
40 nm, and 200 nm respectively (from the left to the right).
In order to find the parameters given in Table 3-5 that can meet the requirements set by the
device concept, an optimization process was carried out by identifying the key parametric
dependences of the anisotropy and sidewall roughness. The temperature was kept at 220 0C
throughout the study, because a good agreement on the temperature exists in the literature.
Normally ICP power in SAMCO system is around 100W, which leads to an etch rate about 1
57
pm/min. For our purpose, it would be too fast because in that case only 15 seconds were needed,
and therefore variations can be large. So the ICP power was lowered considerably down to 20
W, and the total etch time can be around 2 min. The ICP power was found not to affect the
etching profile or sidewall roughness significantly.
To achieve good anisotropy, it is clear from the previous discussions that the bias power,
pressure, N 2 and Cl 2 flow rate need to be balanced carefully. The SEM images shown in Figure
3-8 illustrated such statement. The etching parameters for Figure 3-9 (a), (b) and (c) were shown
in Table 3-6, from column 2 to 4. When the chamber pressure increased from 0.3 Pa in (a) to
0.67 Pa in (b), significant undercut was observed, because particle mean free path was shortened
and therefore more chemical reactive species can travel laterally due to more frequent collisions.
As a result, lateral etching was more pronounced. From (a) to (c), significant undercut was
present when the N2 flow rate was reduced. The reduction of N2 flow resulted in less
passivation of the sidewall, so the balance between passivation and lateral chemical etching was
compromised.
a
C
149nm
330nm
1 pAM
16p
478 nm
740 nm-
Figure 0-9. 150 tilted SEM images of semiconductor pillars etched with parameters specified
in Table 3-6. The HSQ mask thickness was 90 nm for all three cases.
58
Parameter
Gas
Flow Rate (secm)
Pressure (Pa)
ICP Power (W)
Bias Power (W)
Temperature ( C)
Etch Time (min)
Values for (a)
C12/BCl 3/N2
8.8/4.4/26.8
0.3
20
160
220
2
Values for (b)
C12/BCl 3/N2
8.8/4.4/26.8
0.67
20
160
220
2
Values for (c)
C12/BCl 3 /N 2
8.8/4.4/10
0.3
20
160
220
2
Table 0-6. SAMCO ICP RIE parameters for the etch results shown in Figure 3-9 (a), (b) and (C)
One distinct feature from Figure 3-8 was the significant sidewall and surface roughness (or
micromasking). To reduce the roughness and micromasking, a balanced removal rate of Group
III and Group V elements are required. As discussed previously, InClx is harder to remove than
other etching byproducts due to its low volatility, so Indium rich compounds were left on the
surface/sidewall which caused the micromasking/roughness. So physical bombardment induced
by heavy ions provided by BCl 3 should be enhanced with regard to chemical etching resulting
from the chemical reactive species offered by Cl 2 . This is exactly what happened in Figure 3-10,
where Cl 2 flow rate was reduced from 8.8 (on the left) to 0.5 scem (on the right). It can be seen
that the micromasking problem was greatly improved. Other etching parameters were provided
in Table 3-7. As only surface properties were needed, no hard mask was defined in this
comparison. The etching was 15 seconds in both cases. Based upon these findings, further
optimization was performed and the parameter set given in Table 3-5 were reached.
59
no micromasking
micromasking
Figure 0-10. 450 tilted.SEM images with regard to the top view of the semiconductor surface
etched with parameters specified in Table 3-7. No hard mask was defined by EBL for both
cases, since only surface properties were examined.
Parameter
Gas
Flow Rate (sccm)
Pressure (Pa)
ICP Power (W)
Bias Power (W)
Temperature ("C)
Etch Time (min)
Values for the left image
Cl2/BC 3/N2
8.8/4.4/26.8
0.3
20
160
220
2
Values for the right image
C12 /BCl 3 /N 2
0.5/4.4/26.8
0.3
20
160
220
2
Table 0-7. SAMCO ICP RIE parameters for the etch results shown in Figure 3-9
Aside from the various parameters discussed above, there were several other considerations for
this RIE process. Vacuum grease is often used between the carrier and the sample to create a
good thermal contact that allows for better heat transfer between the sample and the heated
wafer carrier. If vacuum grease is not applied, there will be large gaps between the substrate and
the carrier, because neither of them is perfectly flat, meaning that they will only contact at a few
points. One would expect the sample to take a very long time to reach thermal steady state with
the carrier sits in a vacuum chamber. In the actual etching process, during the first 10 minutes
60
no RF power was applied, in order for the sample to reach a thermal steady state.
Experimentally, etching was successful with this 10 minute wait period, even without the
vacuum grease, suggesting that the sample was indeed heated up. Avoiding vacuum grease
allowed for a cleaner process.
A ceramic carrier was used to hold the InP substrate in the SAMCO system. Other researchers
have found that a silicon carrier works for Cl 2 based III-V semiconductors. However, this was
not the case in this study. BCl 3 plasma etches silicon and can sputter silicon elements onto the
substrate, thus effectively passivating the surface by forming polymers. Figure 3-9 showed the
etch result of a line structure following the process flow specified by Table 3-5, but with a 6
inch silicon carrier. The etch rate was found to decrease from 90 nm/minute to 22 nm/minute,
and the sidewall profile was more sloped, suggesting excessive passivation. The size of the
wafer to be etched was found to play a role in this RIE process as well. The etch rate for a 1
mm2 wafer was 90 nm/min, while that for a lcm2 wafer was 80 nm/min.
Figure 0-11. 150 tilted SEM image of a semiconductor fin etched with a 30 nm wide HSQ
line. The parameters for etching were given by Table 3-5.
61
CH 4/H2 chemistry was initially tested prior to the utilization of Cl 2 based chemistry. CH 4 /H2
chemistry is also commonly used in Indium contained compound semiconductors etch, as the
byproducts are volatile even at room temperature [51]. Compared to Cl 2 based chemistry,
CH 4/H2 gases offer slow etch rate (tens of nanometer per second) and smooth sidewall in
general, which are beneficial for our purpose. However, we were not able to obtain a vertical
sidewall profile by this chemistry available at the Plasmaquest system, which is an Electron
Cyclotron Resonance (ECR) Reactive Ion Etcher (RIE). The reason could be that a high
pressure (> 1.5 Pa) is needed to maintain a stable plasma with the Plasmaquest system, so that a
good anisotropy cannot be realized. Figure 3-11 showed the SEM images of a typical etch result,
whose parameters were summarized in Table 3-8. As can be seen from Figure 3-12, a
significant slope was present after the etching. Also note that the drawn HSQ size was 200 nm,
but after the etching the mask size was reduced to 150 nm, meaning significant lateral mask
erosion, which also degraded the slope. The fact that CH 4/H2 chemistry attacks HSQ
aggressively resulted in the considerable lateral mask erosion, as well as a small etch selectivity
of 2-3. Practically, the SAMCO system is more restricted in terms of materials and chemistries
that can be used, and hence better reproducibility is obtained. Due to the above reasons, C12
based chemistry with SAMCO etcher was selected.
Figure 0-12. 150 tilted SEM image of semiconductor pillars etched with HSQ dot of 200 nm
in diameter. The parameters for etching were given by Table 3-8.
62
Value
CH4/H2
9/40
16
200
200
25
27
3
Parameter
Gas
Flow Rate (seem)
Pressure (mTorr)
ECR Power (W)
DC Bias (V)
Temperature ('C)
Etch Rate (nm/min)
Etch Selectivity to HSQ Mask
Table 0-8. Plasmaquest ECR RIE parameters for the etch results shown in Figure 3-12.
3.3.3 Digital Etch
Standard wet chemical etching of Ill-V semiconductors occurs by oxidizing the semiconductor
surface and etching the oxide. Typically this is achieved by submerging the semiconductors in a
liquid mixture consisting of an oxidizing agent and an oxide etching agent. Therefore the
oxidation and etching occur simultaneously, resulting in an etch depth dependent on the length
of time that the semiconductor is exposed to the etchant. Digital etch separates the oxidation and
oxide etching chemical reactions so that each reaction is independent of each other, and etching
occurs by sequential application of the reactants [52, 53]. Because the oxidation chemical
reaction is self-limiting, the etch depth is no longer dependent on the etch time, but is dependent
on the number of etching cycles [53]. The etch depth during each cycle is rather insensitive to
the time for oxidation or etching due to the self-limiting nature of the oxidation step.
After the semiconductor RIE, there will be dry-etching damage to the sidewall, which is
difficult to anneal in compound semiconductors [9, 54]. Digital etch serves the purpose of
trying to remove the dry-etching damage by wet etching. Normal wet etching cannot be used
because it will be difficult to control the etch depth down to a few nanometers in a reproducible
manner. Another benefit of digital etching is to further reduce the diameter of the semiconductor
pillar from sub-20 nm from the RIE process to sub-10 nm regime in a reproducible fashion. One
requirement for the digital etching in this study was the ability to etch InGaAs and InAlAs in
the superlattice region at a comparable depth per cycle to maintain a uniform pillar profile.
63
A typical cycle of digital etching used in this study is summarized in Table 3-9. A difference
was made between "wet digital etching" and "dry digital etching". In the former case, a liquid
oxidizing agent was used, which was usually 30% H2 0 2 . In a dry digital etching, oxygen plasma
via Asher was utilized to oxide the semiconductor. The wet digital etching can remove
semiconductor layers conformally for the same semiconductor material. But different etch
depths per cycle for different materials can be anticipated, considering the fact that wet etching
often etches different semiconductors at different rates.
Figure 3-13 (left) shows a semiconductor pillar right after the RIE. Note that the heteostructure
for this image is shown in Figure 3-14. The same semiconductor pillar after 8 cycles of wet
digital etching using 30% H2 0 2 as the oxidant and 49% HF as the oxide etchant is shown in the
right image. Note that HSQ hard mask and a 30 nm evaporated Molybdenum layer are on top of
the heterostructure (which can be seen more clearly in the right image). The rest of the process
followed the wet digital etching procedure described in Table 3-9. It was clear that the etch
depth per cycle was different for different materials. The AlGaAs etched slower than InGaAs
and GaAs. It is likely that the dry digital etching can solve this problem, because usually plasma
is less sensitive to material compositions. Figure 3-15 (left) shows a semiconductor pillar right
after the RIE, and the heterostructure is the same with Figure 3-2. The same semiconductor
pillar after 7 cycles of dry digital etching using 10% H2 SO4 as the oxide etchant is shown in the
right image. The process is the same as the dry digital etching shown in Table 3-9. The pillar
after the digital etching is still uniform, confirming that the dry digital etching is not sensitive to
material composition.
Process steps
Wet digital etching
Dry digital etching
Oxidation
Oxidant dipping for 1Os
Asher for 3 min, 800 W
Cleaning
20 s DI water rinse, blow dry
Oxide etching
Oxide etchant dipping for 10s
Oxide etchant dipping for 10s
Cleaning
20 s DI water rinse, blow dry
20 s DI water rinse, blow dry
Table 0-9. Digital etching process details.
64
543 nm
513 nm
Figure 0-13. 150 tilted SEM image of semiconductor pillars with 30 nm Molybdenum layer
evaporated onto the heterostructure shown in Figure 3-14. (left) immediately after RIE
process (right) after 8 cycles of wet digital etching, with 30% H2 0 2 as the oxidant and 49%
HF as the oxide etchant.
A'AGaAs, 3 nm
lon,Ga,, .,As,
15 n1m
AloA2Gao,5sAs, 100 nm
GaAs, 200nmri
Figure 0-14. The heterostructure grown on GaAs substrate used for Figure 3-13.
The drawn HSQ mask pattern size was 20 nm. Using this dry digital etching recipe, pillars with
sub-10 nm diameter and an aspect ratio larger than 10 were fabricated. The footing during the
semiconductor RIE process enhanced the mechanical stability. The etch depth per cycle was
estimated to be 1 nm/cycle.
65
23 nm
135 n
m
0
Figure 0-15. 150 tilted SEM image of semiconductor pillars with the heterostructure shown in
Figure 3-2. (left) immediately after RIE process (right) after 7 cycles of dry digital etching,
with 10% H 2 SO 4 as the oxide etchant.
3.3.4 Planarization
In order to put the top contact and isolate the top contact metal from the gate metal, a
planarization technology is needed. Spin-on glass (SOG) materials have been a mainstay as a
low-k inter-metal dielectric with significant planarizing ability in semiconductor devices[55]. In
this study, Hydrogen Silsesquioxane (HSQ) commercialized as FOx@ Flowable Oxide by Dow
Coming was explored for the planarization purpose.
The major different between this SOG
HSQ and the HSQ used for EBL in section 3.3.1 was the spin thickness range. In fact,
researchers have been using SOG HSQ in electron beam lithography [56]. After the ALD gate
metal step, SOG HSQ will be spun on to cover the entire pillar and then etched back to the
66
desired thickness. Immediate after spin, HSQ is usually baked to let the resist flow and cured to
enhance the uniformity and mechanical stability. As discussed in section 3.3.1, the curing
process promotes cross-linking through thermal agitation, and usually takes place in inert
atmosphere to avoid oxidation which will increase the dielectric constant. The etch back process
can be performed through RIE with Fluorine based chemistry.
Process Step
Storage
Process Details
Refrigerate Fox-15 in a plastic container, at 5'C. (Glass container cannot
be used)
Resist spin
Let the resist sit in the room temperature for half an hour to bring the
resist to room temperature. Drop the resist by Polypropylene pipettes to
cover the entire piece, spin at 4000 rpm for 1 min to a thickness of 350 nm
using TRL-Spinner.
Cure
Immediately after spin, complete the melt and flow step by baking the
sample in N2 environment at 150 0C, 200 0C, and 350 0C for 1 minute
each. Cure the resist via baking the sample at 350 C for 1 hour, under N2
purged environment.
Etch back
Thickness measured on a dummy sample by FILMETRICS, and then the
sample is etched by Plasmaquest for a certain amount of time. Etch back
recipe: Plasmaquest, flow rate of CH 4/H 2 = 30/10 sccm, Pressure = 20
mTorr, DC bias: 1OV, ECR Power: 200W, Temperature: 25 0C, Etch
rate= 30 nm/min.
Table 0-10. SOG planarization process details
A typical process flow for planarization with Fox-15 from Dow coming is summarized in Table
3-10. Figure 3-16 illustrated the planarization to a semiconductor fin. The SEM image on the
right is a cross-sectional view, and the image on the right is tilted 150. From this figure, we can
see that the process shown in Table 3-10 has a reasonable planarization effect with a starting
HSQ thickness of 350 nm. The etched back process is able to stop right at the semiconductor
interface. The key to this fabrication step is a reliable way to accurately measure the cured HSQ
thickness. FILMETRICS based on reflectance method is used to measure the film thickness
67
using the calibrated refractive index. We are currently trying to demonstrate this process with
pillars of sub-10 nm diameter.
SOG
200 nmn
Semiconductor
Figure 0-16. (left) Cross-section SEM image after planarization process described in Table 310 was applied to a semiconductor fin (right) 150 tilted SEM image of the same position.
3.4 Summary
In summary, the key fabrication technologies including electron beam lithography, reactive ion
etching, digital etching and planarization for SLS nanowire FET have been developed.
Semiconductor pillars with sub-10 nm diameter, an aspect ratio larger than 10, nearly vertical
and smooth sidewalls have been demonstrated. The idea for a suitable gate technology was
proposed and experimental effort is ongoing.
68
Chapter 4 Conclusions and Suggestions
In this thesis, we devote our efforts towards the analysis and demonstration of the superlatticesource nanowire FET. The device concept was introduced and various device design issues
were identified and discussed. Key technologies have been developed to fabricate sub-10 nm
nanowire pillars. In this chapter, key findings are summarized and suggestions for future work
are provided.
4.1
Summary
The central idea of the SLS-FET is to engineer the carrier density of states. The conventional 60
mV/dec in a MOSFET is caused by the high energy tail of the carriers at the source. If the DOS
can be engineered in a way that it can be cut off at some energy, the turn-on at this cut-off point
will be infinitely sharp in the ideal case. It is well know that a superlattice exhibits minibands
and minigaps in its band structure. The exponential decaying DOS at the edge of a miniband
will sharpen the subthreshold regime in a conventional MOSFET when the superlattice is
inserted between the source and the channel. Simulations performed by Gnani et al. showed that
an InGaAs/InAlAs superlattice can offer respectable performance when incorporated as part of
the source.
In this thesis, quantum simulations of the superlattice band structure have been performed and
good agreement was achieved with literature results. When lateral confinement is applied
transversal to the growth direction by means of nanowire superlattice, subbands will form in
addition to minibands. Our simulations including such effects predict that in order to have
single subband conduction, the diameter of the nanowire has to be below 10 nm. This is the
target of our experimental work.
The device architecture pursued in this work is a vertical transistor with a superlattice inserted
between the channel and the source. A wrap-around-gate is formed by ALD to control the
channel potential. The number of periods of the superlattice affects the sharpness of the
miniband edge. An analytical expression of the subthreshold swing was derived incorporating
69
the effect of non-ideal band edges induced by the finite periods of the superlattice. We found
good agreement of our calculations with the simulated subthreshold swing by Gnani et al.
validating our modeling environment. The superlattice region needs to be heavily doped to
avoid the capacitive coupling with the gate. Non-idealities such as phonon and doping induced
band edges as well as dielectric/semiconductor interface traps were discussed.
We designed a process flow to fabricate III-V nanowire MOSFET. The key fabrication steps
include electron-beam lithography, reactive ion etching, digital etching, planarization and a gate
technology. We have developed several aspect of this process and demonstrated the capability
of fabricating sub-10 nm semiconductor pillars in InP material system through EBL, RIE and
digital etch. A planarization and etch back scheme via spin-on glass material is under
development. A gate technology based on ALD gate metal (WN) and dielectric (A12 0 3/HfO2) is
being investigated.
4.2 Suggestions
4.2.1
Ongoing Research Efforts
The demonstration of SLS nanowire FETs requires further research endeavor. Following the
work in this thesis, current research efforts have been focused on the following aspects:
e
As the essence of this device concept is to engineer the DOS through a superlattice, it
would be useful to experimentally probe its energy filtering capability. To this regard,
the spectral characteristics of electron transport along the growth direction of the
superlattice have to be studied. Ballistic electron emission microscopy (BEEM) is being
investigated, where a STM serves the purpose of injecting electrons with different
energies into the superlattice. The fabrication technology for this measurement was
already developed in this thesis and a heterostructure has been designed. We are now
designing the BEEM experimental setup.
e
For SLS nanowire FETs to be fabricated, a gate technology has to be in place, which
includes the ALD gate metal (WN) and gate dielectric (A12 0 3/HfO2 ) deposition, and
relevant etching techniques. Ideally, three etching recipes are required: a selective etch
70
of HSQ over WN, a selective etch of WN over HSQ and gate dielectric, and a selective
etch of gate dielectric over HSQ. RIE with CH 4/H2 chemistry can be used for the first
etch. NH 40H/H20 2/H20 only attacks WN. A selective etch of gate dielectric over HSQ
is still to be developed. HF based solution is commonly used to etch high-k dielectric
such as A12 0 3 . However, HF based solution attacks HSQ aggressively. For example, the
etch rate of HSQ in 1:100 BOE is still around 240 nm/min, which is too fast to control.
4.2.2
Suggestions for future research
The work in this thesis is the first step toward SLS nanowire FETs. To exploit the potential of
this device concept, different research directions can be pursued, including:
e
The simulations performed by Gnani et al. assumed ballistic transport. In reality, various
scattering mechanisms including phonons can be very important, and even dominant in
some cases [57]. It would be meaningful to develop and incorporate proper models for
scattering that can be incorporated into our simulation environment.
" As discussed in Chapter 2, heavy doping can result in significant band edges by
introducing dopants and random potentials, which can degrade the subthreshold swing.
A proper model to describe these effects is worthwhile to investigate. Experiments to
identify the effect of doping on the band edges should also be conducted.
*
In contrast with the top down method in this work, a bottom up approach can also be
utilized to fabricate the semiconductor pillars that incorporate the superlattice.
Impressive III-V nanowire superlattice growth has already been demonstrated [58].
" In this work, the gate dielectric will be deposited directly on the surface of InGaAs. To
address the issue of dielectric interface, a thin InP layer can be regrown after the pillar
RIE process, acting as a cap.
71
72
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