ELEN 475 Lab 4
Layout Extraction and Verification
1. Introduction
In this lab, you will learn to extract and verify the layout that you designed in the previous lab.
2. Layout Extraction
1.
Open the layout view of the inverter you designed in the last lab. You might want to choose the mini-sized
inverter. Make sure the substrate contacts and pins are connected correctly.
2.
Choose “Verify -> Extract” in the layout window, then extract window appears. Click OK and the extraction
process starts. If the process succeeds, the extracted view is created and shown in Library Manager.
3.
Open the extracted view. You will see the boundary of each layer is extracted. Note the layer poly, find two
small rectangles on it. These two rectangles represent the extracted pmos and nmos transistors. Highlight one
of the transistors and open its property window. You will see it has been extracted as a cell in library
“NCSU_Analog_Parts”. Continue to see its parameters. You can see transistor parameters, such as width,
length, area of drain and source diffusion (ad and as respectively). However, these values are default values in
the library and you cannot change. Close the property window. Click “shift-f”, you will see the real parameters
of each transistor. Note the width and the length of the transistor, make sure if these values are the same with
what you designed in the layout. Click “ctrl-f”, then the original view is restored.
3. Layout Verification
1.
First draw the transistor level schematic for the inverter. Create a new cellview named “cmos.sch” for the
inverter. Open it and draw a schematic view of an inverter in the transistor level. You can use “Add Instances”
and choose nmos4 and pmos4 from NCSU_Analog_Parts directory. Note you have to connect the terminal
“substrate” of the transistor to power or ground. For the power pins, DO NOT use the vdd and gnd symbols.
Instead, create two inputouput pins with the same name as used in the layout design. Make sure that the
direction and the names of all the pins in both the layout and the schematic are the same.
2.
In the extracted view choose “Verifiy -> LVS”, then LVS form pops up. LVS comes from Layout Versus
Schematic. In field “schematic” and “extracted”, fill in proper names of Library, Cell and View. You can click
button “Browse” to do it. Click “Run” to start with LVS.
3.
Note in CIW several messages flashes then shows “LVS job is now started”. Wait for a while and a window
pops up saying whether the LVS job succeeds or failed. If the job succeeds, it does NOT mean that the layout
and the schematic match. All it means that the job has completed.
4.
If the LVS job fails, then click button “Error Display” in LVS window to show error messages. Try yourself to
correct these errors, then run LVS again. If the LVS job succeeds, click button “Output” in LVS window, then
a text file pops up. Check the file and find any unmatched items. You may need to revise your layout or
schematic to make the two views matched. Do not make changes to the extracted view. If you make changes
to layout, run DRC and extract the layout again.
5.
If your job succeeds, you can find the message saying if the netlist matches or not in the output file. The file
contains summaries for instances, nets and terminals. You will have to submit the output file for the lab report.
4. Report Requirements
1. (3 points) Print the extracted view with transistor parameters shown on it.
2. (3 points) Print the LVS output file with the success message.
3. (1 point) Draw a layout of an NAND gate with two inputs, using parameters same with the inverter you drew
before. Print the layout view.
4. (1 point) Extract the layout of the NAND gate, print the extracted view with parameters.
5. (1 point) Draw the transistor-level schematic of the NAND gate, print the schematic view.
6. (1 point) Do LVS for the NAND gate, print the output file.