HW-5
DESIGN OF AN CMOS INVERTER USING
MENTOR GRAPHICS
(EE – 584)
Submitted by
LAKSHMAN KUMAR GOKAVARAPU
Table of Contents
Page
1. Objective and introduction
3
2. Schematic & symbol
4
3. Quicksim Simulation
5
4. Layout
6
5. LVS report
7
6. Parameter extraction
9
7. Accusim
9
8. Conclusion
10
2
OBJECTIVE & INTRODUCTION
The objective of the given assignment is to design and test the working of an
“INVERTER” using Mentor Graphics CAD tool. Following steps were adopted in
designing and testing the circuit.
1. Schematic is designed using Design Architect.
2. Functional correctness of the schematic is tested using Quicksim.
3. Layout corresponding to the schematic is designed using IC workstation.
4. Verification of the layout is done using DRC rules and LVS check.
5. Parameter extraction is done using IC extract.
6. Functional Correctness of the layout is tested using Accusim.
The inverter is realized using CMOS technology. When the input to the inverter is high
the NMOS transistor is ON and the PMOS transistor is OFF (refer to figure 1).So the
output of the inverter is low. When the input to the inverter is low the PMOS transistor is
ON and the NMOS transistor is OFF and the output of the inverter is high. The truth
table of the inverter is given in table-1.
TRUTH TABLE
IN
OUT
Logic 0
Logic 1
Logic 1
Logic 0
Table-1
3
SCHEMATIC & SYMBOL
The transistor level schematic diagram of an inverter is shown in figure 1.In this
schematic there is an NMOS and a PMOS transistor. The source of NMOS transistor is
connected to the ground. The drain of the NMOS transistor is connected to the drain of
PMOS transistor. The source of the PMOS transistor is connected to the power supply.
The gates of both the transistors are connected together and the input is given to the gates
of the transistors. The supply voltage is given 3 volts and the ground is assumed to be 0
volts. The W/L ratio of the PMOS transistor is twice that of NMOS transistor.
figure.1
4
The symbol of the inverter is shown in figure 2.
figure.2
QUICKSIM SIMULATION
The quicksim result of the inverter is shown in fig3. The quicksim is run to verify the
functional correctness of the schematic. In order to test for the functional correctness, all
possible input combinations (0&1) are given and corresponding output for the given input
is verified against the truth table. From figure.3 when the input to the inverter is logic 0,
output is logic 1 and when the input is logic 1, the output is logic 0.
figure.3
5
LAYOUT
The layout corresponding to the schematic is designed in IC station tool of Mentor
Graphics. This tool has the various layers of the design like “Active”,”Poly” etc in the
form of toolbox. This toolbox could be “dragged and dropped” on the layout screen and
then the size of the layers are modified using the various options like “Move”, “Copy”
etc.The layout was designed using a pitch of 50. The “Pitch” is defined as the distance
between the bottom layer of “ground” and upper layer of “VDD”.Figure.4 shows the
mask layout of an inverter. The layout in figure.4 corresponds to schematic in figure.1.
figure.4
6
“DRC (Design Rule Checker) rules” are the rules that define the spacing between various
layers, which should be followed in designing a layout.
The rules are given below:
2-Minimum width of poly.
2-Minimum width and length of contact
2-Minimum extension of poly beyond diff.
1.5-Minimum enclosure of contact by diff.
2-Minimum spacing between contact and poly.
3-Minimum poly-poly interspacing.
After designing the layout, it is then subjected to design rule check (DRC).If the layout
passes through the DRC, then it implies that the layout satisfies all the design rules. The
layout shown in figure.4 successfully passed through the DRC.
LVS REPORT
The vital thing about the layout design is that it should match the circuit schematic. The
layout is said to be correct only if the circuit and layout match in the number of “ports”
and “instances”. This is done by LVS (Layout Versus Schematic) tool. The LVS tool
requests the source (circuit schematic) path & name from the user and compares this with
the layout. If they match then it generates a “SMILY FACE” indicating that the layout is
correct. The LVS REPORT of this project is given in figure.5 and the table in figure.6
indicates the number of ports and instances.
7
figure.5
figure.6
8
PARAMETER EXTRACTION
Parameter Extraction is done to extract and back annotate the “Lumped Parameters”. The
values of Lumped Parameters including the “Intrinsic capacitances and resistances” could
be obtained using this facility.
ACCUSIM
Accusim gives the analog simulation results of the layout.Accusim result of an inverter is
shown in figure.7.In order to test for the functional correctness of the layout, varying
voltage is applied to the input and the output voltage is observed. The layout has been
tested for all possible input voltage swings. Since the input voltage is not digital voltage
there is finite rise time and fall time for the inputs and also there would be rise time and
fall time for the output.
figure.7
9
From the figure.7 it is observed that when the input is 0 volts the output is 3 volts and
when the input is 3 volts the output is 0 volts and hence the output follows the truth able.
CONCLUSION
Thus the CMOS Inverter was simulated using Mentor Graphics with a pitch of 50.The
final layout obtained clearly matched the required objective of having a minimum total
area. Also the rise time and fall time of input and output of the circuit schematic was
found to be nearly equal to 1.7ns.
10