UNIVERSITY OF TEHRAN
Electrical and Computer Engineering Department
ECE 2586
Digital Logic Circuits – Fall 1382-83
Course Outline
Revision 1.2
Saturday lectures are underlined
Homeworks are due at the end of the day on which they are assigned
Computer Assignments are due at the end of week on which they are assigned
CLASS: 1. CHAPTER: 0, 1
LECTURE: Introduction, Design methods, Numbers, Switches.
CLASS: 2. CHAPTER: 1
LECTURE: Numbers, integers, fractional, hex and octal.
CLASS: 3. CHAPTER: 1
HOMEWORK DUE: HW 1; 1.1abd, 1.4af, 1.7c, 1.8ce, 1.10bd, 1.12ac, 1.15, 1.18.
COMPUTER ASSIGNMENT DUE: CA 1; Paper on:
“Digital Systems Hierarchies and Ways of Representing Them”
LECTURE: 2's Complement, Arithmetic, Switch level gates, Overflow circuit.
CLASS: 4. CHAPTER: 2
LECTURE: Switch level, Gate structures, Switch level electronics, Boolean.
CLASS: 5. CHAPTER: 2
COMPUTER ASSIGNMENT DUE: CA 2; Basic structures using switches.
LECTURE: SOP, Minterms, K-Map Basics, 2-Var, 3-Var.
CLASS: 6. CHAPTER: 3
HOMEWORK DUE: HW 2; 2.1b, 2.2c, 2.6b, 2.7ab, 2.12a, 2.15ab, 2.23, 2.25.
LECTURE: 4-Var maps, Simplifications, POS, Maxterms. Verilog coding, NAND,
NOR.
CLASS: 7. CHAPTER: 3
HOMEWORK DUE: HW 3;
1. Write a switch-level Verilog code for a CMOS 2-input XOR, a 2-input NAND gate, and a 3-input
NAND gate. 2. Show switch-level logic for a 3-input MAJ gate. 3. Write Verilog code for a FullAdder; gates of Part 1.
LECTURE: K-Maps, Don't Cares, Simplification, Delay timing, Hazards. Gate level
Verilog.
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CLASS: 8. CHAPTER: 4
HOMEWORK DUE: HW 4; 3.1b, 3.2d, 3.3c, 3.4, 3.9, 3.10, 3.12, 3.13a, 3.30, 3.46.
LECTURE: Quine-McCluskey, don't care. Packages, Decoders, Multiplexers.
CLASS: 9. CHAPTER: 4
HOMEWORK DUE: HW 5; 4.2, 4.6, 4.8, 4.15, 4.19abc, 4.20, 4.24, 4.32.
COMPUTER ASSIGNMENT DUE: CA 3; Gate Level Verilog.
LECTURE: Three-State Logic, MUX Based Design, Parity, Comparators, Iterative
circuits, Adders.
CLASS: 10. CHAPTER: 4
LECTURE: Subtractors, Other MSI parts, ALUs; Combinational Verilog.
CLASS: 11. CHAPTER: 4
HOMEWORK DUE: HW 6; 4.39, 4.40, 4.43, 4.44.
LECTURE: Arrays, Polarity, ROM.
CLASS: 12. CHAPTER: 5
LECTURE: Verilog package description.
CLASS: 13. CHAPTER: 5
HOMEWORK DUE: HW 7; 5.1.
COMPUTER ASSIGNMENT DUE: CA 4; Combinational Verilog.
LECTURE: Cascading ROMs, PLA, PAL. Verilog coding of Array Logic
CLASS: 14. CHAPTER: 6
HOMEWORK DUE: HW 8; 5.2, 5.4.
LECTURE: State representation, Flip-flops, Cross-coupled gates, SR Latch, DFF,
TFF.
CLASS: 15. CHAPTER: 6
HOMEWORK DUE: HW 9; 6.1, 6.4, 6.6, 6.7, 6.10, 6.11, 6.12.
LECTURE: Master-Slave FF, Edge Trigger Flip-flops.
CLASS: 16. CHAPTER: 8
HOMEWORK DUE: HW 10; 6.17, 6.18, 6.26, 6.27, 6.28.
LECTURE: State Machines, Definition, State Diagrams.
T E S T 1, Covers up to Class 14; Topics include Switches, Gates, KM, Verilog,
Minimization, Logic Arrays, Basic Flip-flips.
CLASS: 17. CHAPTER: 8
COMPUTER ASSIGNMENT DUE: CA 5; Latches and Flip-flops.
LECTURE: Sequence detectors, Mealy and Moore Machines.
CLASS: 18. CHAPTER: 8
HOMEWORK DUE: HW 11; 8.1, 8.3, 8.6, 8.10, 8.12, 8.13bc, 8.16.
LECTURE: One-hot and other types of controllers, Verilog, Garage Door Opener.
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CLASS: 19. CHAPTER: 8
LECTURE: Controller implementation, Clock control, Verilog coding.
CLASS: 20. CHAPTER: 8-7
HOMEWORK DUE: HW 12; 8.22a, 8.24, 8.25, 8.26, 8.27.
LECTURE: Counters, binary and random; functional registers.
CLASS: 21. CHAPTER: 7
COMPUTER ASSIGNMENT DUE: CA 6; State Machines.
LECTURE: Counters, types of counters, shifters, Verilog code.
CLASS: 22. CHAPTER: 7
HOMEWORK DUE: HW 13; 7.3, 7.8, 7.10, 7.12, 7.14, 7.15, 7.19.
LECTURE: Counters, Universal shift registers, applications, cascading, applications.
CLASS: 23. CHAPTER: 7
LECTURE: Component based sequential circuit designs, data/control.
CLASS: 24. CHAPTER: 8.3
HOMEWORK DUE: HW 14; 8.28.
LECTURE: A first design example.
CLASS: 25. CHAPTER: 8.3
COMPUTER ASSIGNMENT DUE: CA 7; System Design.
LECTURE: Definition and design of an eight-bit multiplier.
CLASS: 26. CHAPTER: 9
HOMEWORK DUE: HW 15; 8.29, 8.30.
LECTURE: Implication tables.
CLASS: 27. CHAPTER: 9
LECTURE: State minimization; System design
CLASS: 28. CHAPTER: 10
HOMEWORK DUE: HW 16; 9.5, 9.8, 9.10ab.
LECTURE: Asynchronous circuits, Flow tables, TFF example.
CLASS: 29. CHAPTER: 10
COMPUTER ASSIGNMENT DUE: CA 8; Asynchronous Circuits.
LECTURE: Asynchronous circuits, hazards, races; A complete example
CLASS: 30. CHAPTER: 10
HOMEWORK DUE: HW 17; 10.1, 10.2, 10.7, 10.11
LECTURE: More on Asynchronous circuits;
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CLASS: 19. CHAPTER: 8
LECTURE: Controller implementation, Clock control, Verilog coding.
CLASS: 20. CHAPTER: 8-7
HOMEWORK DUE: HW 12; TBA
LECTURE: Counters, binary and random; functional registers.
CLASS: 21. CHAPTER: 7
COMPUTER ASSIGNMENT DUE: CA 6; State Machines.
LECTURE: Counters, types of counters, shifters, Verilog code.
CLASS: 22. CHAPTER: 7
HOMEWORK DUE: HW 13; TBA
LECTURE: Counters, Universal shift registers, applications, cascading, applications.
CLASS: 23. CHAPTER: 7
LECTURE: Component based sequential circuit designs, data/control.
CLASS: 24. CHAPTER: 8.3
HOMEWORK DUE: HW 14; TBA
LECTURE: A first design example.
CLASS: 25. CHAPTER: 8.3
COMPUTER ASSIGNMENT DUE: CA 7; System Design.
LECTURE: Definition and design of an eight-bit multiplier.
CLASS: 26. CHAPTER: 9
HOMEWORK DUE: HW 15; TBA
LECTURE: Implication tables.
CLASS: 27. CHAPTER: 9
LECTURE: State minimization; System design
CLASS: 28. CHAPTER: 10
HOMEWORK DUE: HW 16; TBA
LECTURE: Asynchronous circuits, Flow tables, TFF example.
CLASS: 29. CHAPTER: 10
COMPUTER ASSIGNMENT DUE: CA 8; Asynchronous Circuits.
LECTURE: Asynchronous circuits, hazards, races; A complete example
CLASS: 30. CHAPTER: 10
HOMEWORK DUE: HW 17; TBA
LECTURE: More on Asynchronous circuits;
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