9. Additional Bistable Memory Devices
9. ADDITIONAL BISTABLE MEMORY DEVICES
A basic latch is made from two gates with crossed feedback from outputs to inputs. More
complicated triggers – latches or flip-flops – are formed from a basic latch and a control circuit.
A control circuit can be more complex than basic latch, it can contain another latch or flip-flop.
9.1. Classification of Bistable Memory Devices
Bistable memory devices are classified according some specific features.
According the signals in their informative and control inputs all memory devices can be
divided into three major groups.
1. The first group consists from elementary level-triggered memory devices – latches.
The latches are switched by high and low voltage levels in their informative inputs when high
and low voltage levels in control inputs enable to switch them. There are latches with control
inputs and there are latches without them.
2. Pulse-triggered or master-slave flip-flops form the second group. Signals in the informative inputs switch a flip-flop of this group, when a voltage pulse comes to an end in the
control input of the flip-flop. This property gave another name to the flip-flops of this group:
flip-flops with postponed output – a signal in the output of this flip-flop is postponed till the end
of a pulse in a control input.
3. The third group is made up from edge-triggered flip-flops. Signals in the informative
inputs switch an edge-triggered flip-flop only in the moment of the edge of a pulse in a control
input of the flip-flop.
Within each of these groups, latches or flip-flops of four different structures' can be
constructed.
1. S-R triggers (latches or flip-flops) have two informative inputs: S and R. Active combinations of signals in these inputs SR  10 and SR  01 set and reset the trigger. Combination
SR  00 is passive, it does not change the state of the trigger, combination SR  11 is not
normally allowed.
2. D trigger is a S-R trigger with one informative input D  S. R input in a D trigger is
made as inverted input D. Both signals D  1 and D  0 are active and they are repeated in the
main output of the trigger Q. Passive and not normally allowed combinations SR  00 and
SR  11 are impossible in a D trigger.
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9. Additional Bistable Memory Devices
3. J-K triggers – the triggers with crossed feedback from outputs to inputs. The two
informative inputs J and K are similar to the inputs S and R.
4. T triggers – J-K triggers with one informative input T  J  K.
Another feature lets to divide bistable memory devices in two groups.
1. Asynchronous triggers can be switched in any moment. Their states are determined by
the signals in informative inputs only. Merely the level triggered latches can be asynchronous.
2. Synchronous triggers have informative inputs and control input C. This input
sometimes is named as clock – CK, sometimes as enable – E. Synchronous triggers are
switched by the signals in informative inputs then and only then when a signal in the control
input enables to switch the trigger.
In the sections below we will analyze synchronous triggers only because:
– they are more complex; asynchronous triggers are partial case of synchronous triggers;
– basic asynchronous S-R NOR and NAND latches we analyzed in details in the previous
chapter.
9.2. Gated Latches
In this section we will analyze synchronous level triggered S-R, D, J-K, and T latches. All
synchronous latches have time gates that are ruled by a signal C in a control input. Time gates
let or not let informative signals pass to informative inputs of the gated latches.
9.2.1. S-R gated latches
When the control input signal C is 0, signals applied to S and R inputs are not let to the inputs
of a basic S-R latch. When the control input signal C is 1, S and R signals can reach the inputs
of a basic latch. It is very important that unable signal C  1 would create passive combination
of signals in the output of a gate, that does not change the state of a basic latch. Unable signal
C  0 in the control input catches the information, written to the basic latch; it is obliged not to
change this information. It means that signal C  0 must create a passive combination of signals
in the outputs of the gate – in the inputs of a basic latch.
The AND time gate fulfils earlier formulated requirement: it creates passive combination
S  0 and R  0 for the basic NOR latch when the signal C  0 operates in the control input of
gated S-R latch.
S

SC
1
Q
S

S
R
C
R
C

RC
1
Q
R
Q
Q
S
C
R
Q
Q

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9. Additional Bistable Memory Devices
Synchronous or gated S-R latch according the names of its inputs is called as SRC latch
or SRT latch, so emphasizing that there is a time gate in this latch.
Example 9.1
Draw a logic diagram of the gated S-R latch with basic NAND latch. What technology is the best for this gated
latch?
Example 9.2
Write the characteristic equation for the gated S-R NOR latch. The characteristic equation of the basic NOR
latch is as follows:Q  SR + qR.
Solution
From a logic diagram of the gated latch we can write:
S  SC, R  RC; Q  SCRC + qCR  SC(R + C) + q(R + C)  CSR + qC + qR.
Example 9.3
Fill in a Karnaugh map for the gated S-R NOR latch.
Example 9.4
Obtain the state diagram for the gated S-R NOR latch.
When C  1, an operation of a gated S-R latch is the same as an operation of the basic
latch. For the gated S-R latch combination CSR  111 is not normally allowed.
Example 9.5
Draw a logic diagram of gated S-R latch with basic NOR latch and with additional inputs PR (preset) and CLR
(clear). The signals in inputs PR and CLR must to set and reset the gated latch irrespective of control signal C.
The active signals (1s in direct inputs PR and CLR and 0s in inverted inputs PR and CLR) can not operate
simultaneously. The logic diagram must to guarantee, that in all situations, with the exception of CSR  111,
gated latch remains a trigger: it's outputs are inverted one with respect to another.
Example 9.6
Repeat an example 9.5 for a gated S-R latch with a basic NAND latch.
9.2.2. Gated D Latches
A gated S-R latch can be converted to a D latch by the simple addition of an inverter as shown
in the picture. The inverter provides latch circuit with only one informative input called the data
input. The inverter also insures that S-R latch inputs are complemented so that the signal
condition SR  11 cannot occur. To set the gated D latch requires input signals CD  11, and to
reset – CD  10.
Q
Q
All latch circuits whether they are S-R, D, J-K, or D
S
D
T, have the property of transparency. The transparency C
C
Q
Q
C
property simply means that the outputs respond to an
R
1
input signal change when the control input signal is 1.
For a gated D latch, the data input signal D is transferred to the Q output when C  1, and the Q
output signal follows the data input signal D as long as C remains logic 1.
Example 9.7
Using the characteristic equation for the gated S-R latch with the basic NAND latch Q  S + qR, write the
characteristic equation for the gated D latch.
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9. Additional Bistable Memory Devices
Example 9.8
Using the characteristic equation for the gated D C
latch fill inn it's Karnaugh diagram, and draw the
state diagram.
tsu
th
For proper operation of the latch, the D
data must meet the data setup time tsu, and
data hold time th before and after control
Q
input signal changes. Data that arrives after
the data setup time starts or changes prior to
the data hold time ends, can cause the signal
race condition and erratic operation of the device.
t
9.2.3. Gated J-K Latches
A gate level or logic diagram (a), a functional diagram (b), and a graphic symbol (c) of a gated
J-K latch is shown in the picture.
J
1

Q
J

S
R
C
C
K
1

a
Q
K
Q
Q
Q
J
C
Q
K

b
c
As the gated D latch utilizes an inverter to ensure the basic latch S and R inputs complemented, the gated J-K latch uses gating to steer either the J (jump) input signal or K (keep)
input signal, and thus keep the S and R inputs complemented. Steering is achieved when the
control input C is 1 by allowing only the J input to be enabled when the Q output is 0, and
allowing only the K input to be enabled when the Q output is 1. Thus when the Q output is 0
and the J input is 1, the J input is enabled so that latch can be set. When the Q output and the K
input are 1, the K input is enabled to reset the latch. If the J and K inputs are logic 1 at the same
time, and the control input C  1, the feedback circuit should toggle the output. If the Q output
is logic 1, toggling the output changes it to a 0, and if the Q output is logic 0, toggling the
output changes it to a 1. Unfortunately, the input signal combination CJK  111 provides an
unstable circuit; otherwise, the gated J-K latch has the same properties as the gated S-R latch.
Example 9.9
According the logic or functional diagram on the picture and using the characteristic equation for the gated
S-R latch with the basic NOR latch Q  S R + q R write the characteristic equation for the gated J-K latch.
89
9. Additional Bistable Memory Devices
Example 9.10
Using the characteristic equation for the gated J-K latch fill inn its Karnaugh diagram, and draw the state
diagram.
When CJK  111, the gated J-K circuit oscillates at a frequency determined by the
propagation delays through the circuit. By 'oscillates' we mean that the output repeatedly
changes from 1 to 0, back to 1, back to 0, and so on for as long as the external input conditions
CJK  111 exist. This is not desirable property, and renders the gated J-K latch circuit as practically useless. One possible way to make the circuit perform the toggle function normally is to
use extremely short positive pulses to trigger the circuit at the control input. The duration of this
positive pulse must be shorter than the propagation delay through the circuit – an undesirable
solution in the most cases. Such circuit should toggle each time a positive pulse is applied to the
control input.
9.2.4. Gated T Latch
T

Q
S
R
Q
C

Q
T
C
Q
The gated T latch circuit shown in the picture
suffers the same erratic oscillating property as the
gated J-K latch. Each implementation races from
q  0 to q  1 back to q  0, and so on endlessly,
while the combination of input signals' CT  11
exists. For this reason gated T latch, as gated J-K
latch, is not considered useful circuit configuration.
9.3. Master-Slave Flip-Flops
The master-slave (pulse triggered) flip-flop evolved as a result of trying to solve the problem
associated with oscillating of gated J-K and T latches. Gated-latch circuits cannot be used
simply because of their transparent property. A master-slave flip-flop is designed to interrupt
the logic connection between the inputs and the outputs during the time the input control signal
is a logic 1. Removing the logic connection between the input and output signals the masterslave design provides the following benefits: it reM
S
Q moves the transparency property hence the oscillaS
tion; it provides a memory device, which can be
J
S

C
Q used in synchronous sequential designs, synchroR
R
nized by a system clock.
C
The master-slave J-K flip-flop is made from

1
K
two gated S-R latches connected in cascade, and the
control signal of the second latch is an inverted
control signal of the first latch, which is a control
90
9. Additional Bistable Memory Devices
signal of the flip-flop. The master (the first gated S-R latch) drives the slave (the second gated
S-R latch). The present state outputs of the slave are fed back to the inputs of the master such
that the J input is qualified by qC while K input is qualified by qC, thus allowing the toggle
property. When the external control input signal is logic 1, the master is transparent from its
inputs to its outputs. Because of the inverter, during this same time period the slave is being
disabled (its control input signal is logic 0), and thus is not transparent. By disabling the slave,
the present state output signals from the slave remain stable. In effect, this interrupts the logic
connection between the inputs and the outputs of the device during the time the input control
signal is logic 1. When the external control input signal makes a transition from 1 to 0, the data
present at the J and K inputs are captured, the master is disabled, and the slave is enabled.
Changes at the master's inputs are of no consequence at this time since it is now disabled and its
outputs are stable. The slave is now transparent, but the master is supplying it with stable
inputs. After a short delay time of t, the slave's outputs also become stable. Since the master is
disabled, feedback around the entire circuit is interrupted again. The race condition is
eliminated by this cascaded approach, allowing the master-slave flip-flop to toggle only once
for each external control signal pulse.
Because the master-slave principle utilizes both edges of the
Postponed output
Q symbol
external signal applied to the control input, this type of flip-flop is a
J
pulse triggered bistable. The graphic symbol for a standard masterC
Q
slave (pulse-triggered) J-K flip-flop is represented on the picture.
The postponed output symbols shown inside the rectangular symbol
K
of the master-slave flip-flop indicate that the next state value of the
output is postponed until the external control signal returns to its 0 logic state.
Observing the timing diagram on the picture, one can see that the master-slave J-K flipflop on the timing events 2 and 3 is normally set (J  1 and K  0 before C changes from 0 to
1). On the timing events 5 and 6 the master-slave J-K flip-flop is normally toggled (J  1 and
K  1 before C changes from 0 to 1). On the timing events 10 and 11 the master-slave J-K flipflop catches 1 (J becomes 1 after C changes from 0 to 1). On the timing events 14 and 15 flipflop catches 0 (K becomes 1 after C changes from C
0 to 1).
Example 9.11
J
Draw the timing diagrams illustrating the normal reset of
the master-slave J-K flip-flop.
The 1s catching or 0s catching property of
master-slave (pulse-triggered) flip-flops can result
in improper circuit operation. Improper operation
occurs when the external input signals have not
become stable (reached a steady state condition)
prior to the 0 to 1 transition of the control input
signal. To avoid improper operation of master-
K
M
Q
t
1 2
3 4
5
6 7 8 9 10
12 13 15
91