Master electronics interface document
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University of Leicester PLUME Ref: PLM-SYS-MasterElectronics-605-6 Date: 19/04/2010 Master electronics interface document Philip Peterson Date 11/08/2009 17/08/2009 Updated Reference Number PLM-SYS-MasterElectronics-605-1 PLM-SYS-MasterElectronics-605-2 19/08/2009 20/08/2009 PLM-SYS-MasterElectronics-605-3 PLM-SYS-MasterElectronics-605-4 29/10/2009 PLM-SYS-MasterElectronics-605-5 19/04/2010 PLM-SYS-MasterElectronics-605-6 [dd/mm/yyyy] [PLM-XXX-XXX-xxx-x] Change Initial version Altered pin designations to place high frequency camera pins away from analog signals Edited formatting Corrected payload pin designation. Moved PAY HV_SET from H1.10-12 to H1.6-8 and SIGNAL_Y from H2.2 to H2.8. Added OBDH controls to H1.10-11 and H2.2. Removed pin assignment due to burned out pin on development board (H2.1), updated COMS and Payload assignments [eg. first draft] Introduction This master document details which pins on the satellite’s PC-104 connector are allocated to what subsystem. Its purpose is to reduce the chance of incompatible subsystem pin allocation by providing a central record. Any clashes or desired changes should be reported to the systems engineer, Daniel Brandt as of this writing. Page 1 of 5 University of Leicester PLUME Ref: PLM-SYS-MasterElectronics-605-6 Date: 19/04/2010 Definition of terms Pin ID: The satellite bus uses a PC104 style connector, but it does not use the standard PC104 pin designations. The PC104 connector has two ‘blocks’, H1 and H2, each with 52 pins, the layout of which is shown below. Pins are numbered in a zigzag pattern H1.51 H1.52 H2.51 H2.52 H1 H2 H1.1 H1.2 H2.1 H2.2 Description: The pin’s name and purpose. For a more thorough explanation, see the allocated system’s documentation. Link: An important field describing which two subsystems are communicating using the pin, and which is actually controlling the voltage on it. The field has the format ‘controller>recipient’. If the link is both ways (as with I2C) then format will be ‘one<>other’. Outputs or inputs that are defined by the owning subsystem but are not used to interface with the others will have ‘???’ as the recipient or controller. So, for example, a pin carrying ADCS analog signal data to the ADC on the MCU would be labelled ‘ADCS>OBDH’. The OBDH team would see this as an input pin, and ADCS would see it as an output pin. A plus symbol means more than one subsystem uses the pin; specifics will be given in the pin description. Format: Identifies which voltages should be used on the pin. The maximum current that the pin can source is given afterward in parentheses. 5V Logic: Logic pin with 5V representing binary 1 and 0V representing binary 0. 3.3V Logic: Logic pin with 3.3V representing binary 1 and 0V representing binary 0. These pins can withstand between -0.3V and 3.6V. The power draw from the OBDH board should not exceed 48mA for all the 3.3V TTL pins combined. 5V Power: 5V regulated power pin. 3.3V Power: 3.3V regulated power pin. Digital ground: 0V for logic signals Analog ground: 0V for using the ADC; keep this separate from the other two. Battery: Unregulated direct output from the batteries, in the region of 7V to 10V. I2C: Voltages on this pin are compatible with the I2C protocol. In all cases, the OBDH system is the master device. 5V analog: Analog signal pin that swings between 0V and +5V. Page 2 of 5 University of Leicester PLUME Ref: PLM-SYS-MasterElectronics-605-6 Date: 19/04/2010 ±2.5V analog: Analog signal pin that swings between -2.5V to +2.5V. This voltage range is the only one compatible with the MCU’s ADC. 2.5V Reference: A regulated voltage used to calibrate the ADC during a conversion. It is regulated, but is not for supplying power. Switch: These terminals are connected to either the remove-before-flight or the launch switches. If a board is fabricated that connects 3.3V one throw, 0V to another and an I/O port to the common connection then we could detect the state of the switch after launch. Link: These pins are used to carry signals that are eventually destined to be connected onto a different pin. In the current configuration, they are used to carry high frequency digital signals from the camera down through the satellite bus to the COMS board, where they are connected to an I/O port pin. This is to keep the noisy digital signals away from the analog/digital converter. Owner: This is the subsystem to contact about the pin’s designation. Cons.: The subsystem the ‘constrains’ the pin specification. For example, the power supply has a maximum amount of current that can be drawn from the power supply pins; other subsystems must work to these limits. So the power pins are ‘constrained by’ the PSU subsystem. Page 3 of 5 University of Leicester PLUME Ref: PLM-SYS-MasterElectronics-605-6 Date: 19/04/2010 Pin allocation table Pin ID H1.1 H1.2 H1.3 H1.4 H1.5 H1.6 H1.7 H1.8 H1.9 H1.10 H1.11 H1.12 H1.13 H1.14 H1.15 H1.16 H1.17 H1.18 H1.19 H1.20 H1.21 H1.22 H1.23 H1.24 H1.25 H1.26 H1.27 H1.28 H1.29 H1.30 H1.31 H1.32 H1.33 H1.34 H1.35 H1.36 H1.37 H1.38 H1.39 H1.40 H1.41 H1.42 H1.43 H1.44 H1.45 H1.46 H1.47 H1.48 H1.49 H1.50 H1.51 H1.52 H2.1 H2.2 H2.3 H2.4 H2.5 H2.6 H2.7 H2.8 Description I/O Port 5.7: ADCS_RESET: Set./reset function for ADCS. I/O Port 5.6: OE_MHX: Controls transceiver interface I/O Port 5.5: MAX_10: ADCS axis select MSB I/O Port 5.4: Unassigned I/O Port 5.3: MAX_9: ADCS axis select LSB I/O Port 5.2: HV_SET_x4: High voltage transformer control DAC bit 2 I/O Port 5.1: HV_SET_x2: High voltage transformer control DAC bit 1 I/O Port 5.0: HV_SET_x1: High voltage transformer control DAC bit 0 I/O Port 4.7: COMS I/O Port 4.6: ON_+5V: Controls transceiver interface power I/O Port 4.5: ON_SD: Controls SD card power I/O Port 4.4: COMS I/O Port 4.3: SIGNAL_ON_X: Hold high to enable X detector support. I/O Port 4.2: SIGNAL_ON_Y: Hold high to enable Y detector support I/O Port 4.1: HV_ON_X: Hold high to turn on X HV transformer I/O Port 4.0: HV_ON_Y: Hold high to turn on Y HV transformer I/O Port 3.7: CAM SCC B (formally Camera clock (SIO_C)) I/O Port 3.6: CAM SCC B (formally Camera data (SIO_D)) I/O Port 3.5: Camera VSYNC, goes high when new frame starts I/O Port 3.4: Camera HREF, goes high for new pixel row I/O Port 3.3: Alternate I2C clock I/O Port 3.2: Camera PCLK, goes high for each pixel byte I/O Port 3.1: Alternate I2C data I/O Port 3.0: ON_I2C: Controls offboard isolator for I2C -FAULT: High for OK, low for overcurrent fault. Scans SENSE. VREF+: internal positive voltage reference for ADC SENSE: OBDH supply current = (+5V_SYS - SENSE)/0.075Ω VEREF+: External reference voltage for ADC -RESET: Reset supervisor. Normally low; set high to reset MCU VREF-: External reference voltage for ADC OFF_VCC: Normally low; set high to disable MCU’s 3.3V bus +5V_USB: Power from USB port, present when USB connected. +5V_SW: Power for COMS transceiver, controlled by OBDH. Unassigned (formally -RST_MHX: Transceiver reset, active when low) Unassigned (formally -CST_MHX: Transceiver clear to send, active when low) Unassigned (formally -RTS_MHX: Transceiver request to send, active when low) Unassigned (formally -DSR_MHX: Transceiver data set ready, active when low) Unassigned (formally -DTR_MHX: Transceiver data terminal ready, active when low) Unassigned (formally TXD_MHX: Transceiver transmit data, idles high) Unassigned (formally RXD_MHX: Transceiver receive data, idles high) Unassigned (formally SDA_SYS: I2C Data) VBACKUP: Battery backup voltage. Unassigned (formally SCL_SYS: I2C Clock) Reserved by pumpkin Reserved by pumpkin Reserved by pumpkin Camera data Y7 link: Connect to H2.17 on COMS board Camera data Y6 link: Connect to H2.18 on COMS board Camera data Y5 link: Connect to H2.19 on COMS board Camera data Y4 link: Connect to H2.20 on COMS board Camera data Y3 link: Connect to H2.21 on COMS board Camera data Y2 link: Connect to H2.22 on COMS board PIN NO LONGER IN USE AS IS NOW NON FUNCTIONAL (previously: I/O Port 6.7: SIGNAL_X: Payload X detector signal output) I/O Port 6.6: SIGNAL_X: Payload X detector signal output (formally OE_MHX: Controls transceiver interface) I/O Port 6.5: READ_ADCS: Magnetic strength, use with H2.20, H2.22 I/O Port 6.4: HV_IN_X: X detector HV input sense I/O Port 6.3: HV_IN_Y: Y detector HV input sense I/O Port 6.2: HV_OUT_X: X detector HV output sense I/O Port 6.1: HV_OUT_Y: Y detector HV output sense I/O Port 6.0: SIGNAL_Y: Payload Y detector signal output Page 4 of 5 Link OBDH>ADCS OBDH>OBDH OBDH>ADCS OBDH>ADCS OBDH>PAY OBDH>PAY OBDH>PAY COMS>OBDH OBDH> OBDH OBDH> OBDH COMS>OBDH OBDH>PAY OBDH>PAY OBDH>PAY OBDH>PAY OBDH>CAM OBDH<>CAM CAM>OBDH CAM>OBDH OBDH>PSU CAM>OBDH OBDH<>PSU OBDH>PSU OBDH> ??? OBDH>OBDH OBDH> ??? ??? >OBDH OBDH>OBDH ??? >OBDH ??? >OBDH USB>OBDH OBDH>COMS OBDH>COMS COMS>OBDH Format (mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) I2C (6mA) 3.3V Logic (6mA) I2C (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 2.5V Reference 5V Analog ( ? ) 2.5V Reference 3.3V Logic (6mA) -2.5V Reference 3.3V Logic (6mA) 5V Power (500mA) 5V Power (see H2.25) 5V Logic 5V Logic Owner ADCS OBDH ADCS None ADCS PAY PAY PAY COMS OBDH OBDH COMS PAY PAY PAY PAY CAM CAM CAM CAM OBDH CAM OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH COMS COMS Cons. OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH COMS COMS OBDH>COMS 5V Logic COMS COMS COMS>OBDH 5V Logic COMS COMS OBDH>COMS 5V Logic COMS COMS OBDH>COMS COMS>OBDH OBDH<>PSU OBDH> ??? OBDH>PSU X X X CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH 5V Logic 5V Logic I2C 3.3V Power I2C X X X Link Link Link Link Link Link COMS COMS PSU None PSU X X X CAM CAM CAM CAM CAM CAM COMS COMS PSU OBDH PSU X X X OBDH OBDH OBDH OBDH OBDH OBDH PAY>OBDH ±2.5V Analog PAY OBDH ADCS>OBDH PAY>OBDH PAY>OBDH PAY>OBDH PAY>OBDH PAY>OBDH ±2.5V Analog ±2.5V Analog ±2.5V Analog ±2.5V Analog ±2.5V Analog ±2.5V Analog ADCS PAY PAY PAY PAY PAY OBDH OBDH OBDH OBDH OBDH OBDH University of Leicester Pin ID H2.9 H2.10 H2.11 H2.12 H2.13 H2.14 H2.15 H2.16 H2.17 H2.18 H2.19 H2.20 H2.21 H2.22 H2.23 H2.24 H2.25 H2.26 H2.27 H2.28 H2.29 H2.30 H2.31 H2.32 H2.33 H2.34 H2.35 H2.36 H2.37 H2.38 H2.39 H2.40 H2.41 H2.42 H2.43 H2.44 H2.45 H2.46 H2.47 H2.48 H2.49 H2.50 H2.51 H2.52 PLUME Description I/O Port 1.7: Unassigned, controls FM430 USB interface I/O Port 1.6: COMS I/O Port 1.5: COMS I/O Port 1.4: RESET_X: Payload X detector sample hold reset I/O Port 1.3: RECIEVED_X: Payload X detector signal received I/O Port 1.2: RESET_Y: Payload Y detector sample hold reset I/O Port 1.1: RECIEVED_Y: Payload Y detector signal received I/O Port 1.0: CAM_EN: Hold high to enable the camera I/O Port 2.7: Camera data Y7 I/O Port 2.6: Camera data Y6 I/O Port 2.5: Camera data Y5 I/O Port 2.4: Camera data Y4 I/O Port 2.3: Camera data Y3 I/O Port 2.2: Camera data Y2 I/O Port 2.1: Camera data Y1 I/O Port 2.0: Camera data Y0 +5V power to OBDH, ADCS, COMS +5V power to OBDH, PAY +3.3V VCC_SYS power to OBDH, CAM +3.3V VCC_SYS power to OBDH GND: Digital ground for payload GND: Digital ground for CAM AGND: Analog ground, connected through OBDH to ADCS, PAY GND: Digital ground, ADCS s0 RBF switch normally closed terminal s0 RBF switch normally closed terminal s1 Launch switch normally closed terminal s1 Launch switch normally closed terminal s2 RBF switch normally open terminal s2 RBF switch normally open terminal s3 Launch switch normally open terminal s3 Launch switch normally open terminal s4 RBF switch common terminal s4 RBF switch common terminal s5 Launch switch common terminal s5 Launch switch common terminal VBATT: Unassigned VBATT: Unassigned Unassigned (formally Camera data Y1 link: Connect to H2.23 on COMS board Unassigned (formally Camera data Y0 link: Connect to H2.24 on COMS board) Unassigned (formally Camera VSYNC link: Connect to H1.19) Unassigned (formally Camera HREF link: Connect to H1.20) Unassigned (formally Camera PCLK link: Connect to H1.22) Floating Page 5 of 5 Ref: PLM-SYS-MasterElectronics-605-6 Date: 19/04/2010 Link OBDH> ??? COMS>OBDH COMS>OBDH OBDH>PAY PAY>OBDH OBDH>PAY PAY>OBDH OBDH>CAM CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH CAM>OBDH PSU> + PSU> + PSU> + PSU>OBDH PSU>PAY PSU>CAM OBDH> + PSU>ADCS OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? OBDH> ??? PSU> ??? PSU> ??? Format (mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) 3.3V Logic (6mA) +5V Power +5V Power +3.3V Power +3.3V Power Digital ground Digital ground Analog ground Digital ground Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Switch Unregulated Unregulated Owner OBDH COMS COMS PAY PAY PAY PAY OBDH CAM CAM CAM CAM CAM CAM CAM CAM ADCS PAY CAM OBDH PAY ADCS OBDH None OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH PSU PSU None Cons. OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH PSU PSU PSU PSU PSU PSU PSU PSU OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH OBDH PSU PSU OBDH None OBDH None None None None OBDH OBDH OBDH
