Engr434 - Lab Exercise #4
D Flip-flop Layout
Revised 4/17/2015
Objective
The goal of this lab is to design, layout, and characterize your edge-triggered D-type Flip-flop with
asynchronous set and reset inputs.
References
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Previous lab handouts;
Textbook page 397, and other pages as necessary;
Mosis SCMOS design rules;
Course web page.
Procedure
In this lab you will complete the following steps:
 Layout your 2-input tri-state NAND gate;
 Re-layout your inverter (possibly);
 Layout your D Flip-flop.
Layout your Transmission Gate (if not already completed)
Refer to your schematic design for your D Flip-flop, and all of its components, from one of your previous
lab periods.
Step 1: Using the tutorial from lab #3, layout your transmission gate. Note that you probably want to
make all of your leaf cells from now on to be of equal height and variable width. Make VDD go from
edge-to-edge across the top, GND go from edge-to-edge across the bottom, and P- and N-wells go from
edge-to-edge also.
Step 2: This step is optional, but may save some work when you figure out how to use it. To place VDD
and GND rails with ports and the corresponding NWELL and PWELL layers, type pr and press Return.
The lower left corner of the GND rail will be at location (0,0) and the upper left corner of the VDD rail
will be at (25,120).
Step 3: Do a Design Rule Check (DRC) and fix any errors that occur.
Step 4: Add Port labels.
Step 5: Perform an LVS check.
Step 6: You do not have to do a full characterization, i.e. measuring rise, fall, and delay times, but you are
welcome to do so if you wish.
Step 7: Check and save your schematic and layout.
Layout your 2-input NAND Gate (if not already completed)
Step 1: Repeat the above process for your 2-input NAND gate.
Layout your 2-input Tri-state NAND Gate
Step 1: Repeat the above process for your 2-input Tri-state NAND gate.
Re-layout your Inverter
This step is optional, but if you want your inverter height to match the height of your other leaf cells, then
you need to perform a re-layout.
Layout your D Flip-flop
Step 1: Follow the same process that you used for the three cells above. Note that when you create the
schematic-driven-layout, you will see your cells placed at the hierarchy level of where your port
connections are. This means that you must simply go through the same process as before, only now you
are working at a hierarchy level where the standard cell information is abstracted by one (or more) layers.
Step 2: Place your VDD and GND traces appropriately. You will want to create your VDD and GND
traces at this level of hierarchy using the Metal2 layer.
Step 3: To connect the metal1 layer to the metal2 layer, use a via. A via is created by drawing a 2x2µ box
of type VIA over the intersection of the metal1 and metal2 layers. To place this via, select Objects > Add
> Via > Active Via In the pop-up window, choose the via option (not via2) and click OK. Choose the
location you want and left-click to place the via.
Step 4: Make connections between your high-level ports and cells as appropriate. Use Metal1 layer as
much as possible.
Step 5: Perform DRC and LVS checks. Check and save.
To Turn in
Each person must staple the following items together and turn them in by class time on the Monday
following lab:
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This handout;
A schematic diagram of each cell;
A schematic diagram and symbol of your D flip-flop;
Color printouts of the layout of your D Flip-flop, one showing all layers and a second showing only
the top layer. Write the cell size, in microns, on each cell that you print out.