S.NO
VLSI (B.Tech.)
Projects Titles(2014-2015)
HDL
1
Design of FIR Filter Design Based on Faithfully Rounded Truncated MCM
VERILOG
2
Implementation of JPEG2000 using DWT
VERILOG
3
FPGA implementation of multi operand redundant adders
VERILOG
4
Multi bit Flip-Flop design for Area efficiency
VERILOG
5
MDC FFT/IFFT Processor With Variable Length
VERILOG
6
Built in generation of functional broadside tests using a fixed hardware structure
VERILOG
7
Constant and high speed adder design using QSD number system
VERILOG
8
Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool
VERILOG
9
A Common Boolean Logic(CBL) implementation for modified CSLA
VERILOG
10
High speed vedic multiplier using barrel shifter
VERILOG
11
Comparative analysis and optimization of active power and delay of 1-bit full adder at 45nm technology
BACK END
12
A new approach to design fault coverage circuit with efficient hardware utilization for testing applications
VERILOG
13
Design of Parallel Carry-Save Pipelined RSFQ Multiplier
VERILOG
14
Single phase clock distribution using VLSI technology for low power
VERILOG
15
Design and implementation of efficient Quaternary Signed Digit Multiplier
VERILOG
16
High Speed FPGA implementation of FIR Filters for DSP Applications
VERILOG
17
Design and implementation of Floating Point Multiplier based on Vedic Multiplication Technique
VERILOG
18
A Novel Approach for parallel CRC generation FOR High Speed Application.
VERILOG
19
High speed Modified Booth Encoder multiplier for signed and unsigned numbers.
VERILOG
20
Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation.
VERILOG
21
Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept
using Verilog and FPGA
VERILOG
22
Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra
VERILOG
23
A Floating point Fused Dot Product Unit
VERILOG
24
Implementation of Power Efficient Vedic Multiplier using DBNS
VERILOG
25
LUT Optimization for Memory-Based Computation
Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution based on Fast FIR
Algorithm
VERILOG
26
VERILOG
27
Measurement and evaluation of power analysis attacks on Asynchronous S-Box.
VERILOG
28
High Speed Booth Encoded Multiplier to Minimize the Computation time
VERILOG
29
Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation.
30
VLSI design Of a Digital Clock Using GALS Technique
VERILOG
31
Efficient Weighted Pattern Generation Technique with Low Hardware Overhead
VERILOG
32
SCA-FF and SCAh-FF design for single cycle access test
VERILOG
33
34
35
Design and implementation of a high performance multiplier using HDL
A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth Algorithm
Platform-Independent Customizable UART Soft-Core
A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms by Using Spurious
Power Suppression Technique
VERILOG
37
Using Self-Immunity Technique 64-bit Register File Immunity Improvement
VERILOG
38
A Novel Nanometric Parity Preserving Reversible Vedic Multiplier
VERILOG
39
High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based wavelet Transform
VERILOG
40
Pulse Triggered Flip-Flop Design for low power
BACK END
41
Faster and Low Power Twin Precision Multiplier
VERILOG
42
Design and Analysis of Low Power Parallel Prefix VLSI Adder
VERILOG
43
44
45
46
FPGA Implementation of Booth’s and Baugh- Wooley Multiplier
Implementation of Area Efficient 16bit Adder in FPGA
Reliable and Higher Throughput Anti-Collision Technique for RFID UHF Tag
Implementation of Bus Bridge between AHB and OCP
VERILOG
47
VLSI Implementation of OLS encoders
VERILOG
48
49
Implementation of OFDM System using IFFT and FFT
An Efficient FPGA implementation of Double Precision floating Point Multiplier
50
FPGA Based High Speed Parallel Cyclic Redundancy Check
VERILOG
51
High speed carry save multiplier based linear convolution using Vedic mathematics
VERILOG
52
FPGA Implementation of 2-D DCT Architecture for JPEG Image Compression
VERILOG
53
Performance Evaluation of Complex Multiplier Using Advance Algorithm
54
Design of High Speed Vedic Square by using Vedic Multiplication Techniques
VERILOG
55
Realization of Basic Gates Using MUX in CMOS Design
BACK END
56
A Verilog Model of Universal Scalable Binary Sequence Detector
VERILOG
57
Hardware modeling of binary coded decimal adder in field programmable gate array
VERILOG
58
High-Performance High-Valency Ling Adders
VERILOG
59
Short Bit-Width Twos Complement Multipliers
VERILOG
60
Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics.
VERILOG
36
VHDL
VERILOG
VHDL
VERILOG
VERILOG
VERILOG
VHDL
VHDL
VHDL
VHDL