CSE120
SALESH ASWANI
ID: - 993 - 70 - 9953
PROFESSOR: - MR. MATAR
CLASS: - MWF 8:40
SIMULATION LAB # 2: - 4 BIT FULL
ADDER, MULTIPLEXER & DECODER.
INTRODUCTION
In this Lab exercise we will continue constructing modules that will eventually be used in
assembling the microprocessor. Our concern in this laboratory exercise is with circuits that can
perform binary addition (the adder) and with circuits that control the flow of data through our system
(the multiplexer and decoder). We will eventually use the data-flow-control circuits created in this
lab exercise to make the microprocessor self-capable of routing data to appropriate locations. The
binary addition circuitry we created (which is a 4-bit full adder) will contribute as another piece to
the ALU. Each circuit you build will be modularized by imbedding it in a subcircuit and these
modules will be used in subsequent labs to create more complex circuits.
Equipment: Personal computer and LogicWorks™.
Objectives: In this experiment, we will build and debug combinational logic subcircuits that
perform arithmetic operations and data routing using LogicWorks™.
Outcomes: When you have completed the tasks in this experiment you will be able to design,
build, test, debug, and imbed in a subcircuit, the following:
• A 1-bit full adder.
• A 4-bit full adder.
• A 2-to-1 multiplexer.
• A 4-bit, 2-to-1 multiplexer.
• A 1-to-2 decoder.
• A 2-to-4 decoder.
• A 4-to-16 decoder.
Task 2-1: Design a Full Adder Using NOR/NOR Logic
In this task we have to write down the canonical POS expressions for the Cout and SUM functions
of a Full Adder and then design a full adder using NOR/NOR logic. First we make Karnaugh maps
form the table shown below: -
Karnaugh maps for the above table are (Karnaugh maps made, so that we can form a POS functions
for Cout and SUM):
THE POS FUNCTION FOR Cout FORMED FROM THE ABOVE GIVEN KARNAUGH MAP IS:
Cout = (A + B)
. (B + Cin) . (Cin + A)
THE POS FUNCTION FOR SUM FORMED FROM THE ABOVE GIVEN KARNAUGH MAP:
SUM = (A + B + Cin)
. (A + B’ + Cin’) . (A’ + B’ + Cin) . (A’ + B + Cin’)
1
0
A
A'
B'
Cin
1
1
0
B
B'
Cin'
A
1
0
Cin
Cin'
A'
B
A
B
Cin
1
FULL ADDER CIRCUIT USING NOR GATES AND GATE EQUIVALENCY.
WHAT I LEARNT
In this task I learnt how to build a full adder circuit using NOR gates and gate Equivalency.
Task 2-2: Build, Debug and Test a 1-Bit Full Adder
In this task we have to build, debug and test a 1- Bit Full Adder. I have to use NOR / NOR logic to
implement my minimal POS form for the Cout function and construct the SUM function using either
2, 2 input XOR gates or 4 input XOR. After we make the circuit I have to imbed it in to a sub circuit
that is to be named FA_1 and add it to my library. Then I have to test this sub circuit and write out a
truth table for it.
1
0
1
0
1
0
1
The 1-Bit Full Adder With 2 XOR Gates for SUM And Using NOR /NOR logic For
Cout.
1
The truth table for the above given 1-Bit Full Adder circuit is:
The imbedded version of the 1-Bit Full Adder circuit.
FA_1
1
0
1
0
1
0
A
SUM
0
Cout
1
B
Cin
The truth table that shows that the Sub Circuit works correctly is given below:
WHAT I LEARNT
In this task I realized that instead of using 4 NOR gates to find the SUM (The circuit drawn in task 2.1) I
should have used two XOR Gates (Exclusive – OR gates). That would have been more convenient and
more economical. It would also reduce the gate delays. I did not debug this circuit because there was
nothing wrong with it. While I was making the circuit I took care of the slightest detail so that there would
be no errors in the circuit. And I will not have to waste my time debugging it.
Task 2-3: Design, Build and Test a 4-Bit Full Adder
In this task we have to build and test a 4 – Bit Full Adder circuit. The 4 – Bit Full Adder should
accept two 4 – Bit numbers and a carry as input, and give one 4 – Bit sum and a 1 - Bit Carry as
output. This circuit has to be tested by using a Hex keyboard and Hex display. The design of the
4 – Bit Full Adder is shown below: -
FA_1
A
0
4
8
C
1
5
9
D
2
6
A
E
3
7
B
F
FA_1
SUM
B
0
4
8
C
1
5
9
D
2
6
A
E
Cin
A
SUM
FA_1
A
SUM
B
Cout
1
0
FA_1
A
B
Cout
SUM
B
Cout
Cin
Cin
1
Cout
Cin
3
7
B
F
8
I tested the above given 4 – Bit Full Adder Using a Hex Keyboard and Hex Display. The truth table
that shows that the circuit works correctly is given below:
A
1
E
2
A
6
F
C
B
2
6
F
D
8
4
C
Cin
0
0
0
0
0
1
0
SUM Cout
3
0
4
1
1
1
7
1
E
0
4
1
8
1
The above table proves that the circuit works perfectly. Lets test the out put for inputs of A=1, B=2
Cin=0. This means that an addition is carried out of the three inputs and we get the SUM and Cout.
The addition of the three inputs is shown below:
0001
0010
0
0011
The Addition shows that SUM=3 and Cout = 0.
Hence the 4 – Bit Full Adder Works correctly.
The Sub Circuit of the 4 – Bit Full Adder is given below
FA_4
A3
A2
A1
Y3
A0
Y2
Y1
B3
Y0
B2
B1
Cout
B0
Cin
Task-4: Design, Build and test a MUX Using NOR/NOR logic
In this task we have to Design, Build and Test a Multiplexer Using NOR/NOR logic. We can test the
Multiplexer by comparing the out of the circuit with the truth table given in the CD. The circuit that is to
be imbedded in the Sub Circuit of MUX_1 is shown below:
B
A
A/~B
Y
The Truth table used to verify that the circuit works correctly is given below:-
Below is the imbedded version of the Multiplexer Circuit.
MUX_1
1
0
A
1
0
B
1
0
A/~B
Y
1
Task 5: Build a 2-Input 4-Bit Multiplexer
MUX_1
A
A
A/~B
1
0
0
Y
B
0
1
B
0
1
0
1
1
0
A/~B
A
0
Y
MUX_1
A
1
B
MUX_1
A/~B
1
Y
B
0
1
MUX_1
0
1
0
1
0
1
In this task we have to build and test the 4-Bit Multiplexer. The design of the 4-Bit Multiplexer is
shown below with the inputs and outputs.
A/~B
Y
Below is the imbedded version of the 4-Bit Multiplexer.
MUX_4
A3
A2
A1
Y3
A0
Y2
B3
Y1
B2
Y0
B1
B0
A/~B
Task 6: Build and Test a 1-to2 Demultiplexer using NOR/NOR logic
In this task we have to design a 1-Bit Demultiplexer using NOR/NOR logic. After we design a
Demultiplexer we have to make 4-Bit Demultiplexer. Which is then imbedded into MUX_4 Sub
circuit and saved in to MyLibrary. We imbed the circuits, so that they can be used in making a
microprocessor. Below is the Demultiplexer circuit:
Y/~Z
D
The truth table table that shows the result we are suppose to get from the
Demultiplexer is given below:
Y
Z
This is the imbedded version of the 1 – Bit Demultiplexer
DMUX_1
Y/~Z
Z
D
Y
Task 7: Repackage the 1-to-2 Demux as a 1-to-2 Decoder
In this task we have to imbed a DMUX in to the Decoder. The Decoder that is shown below contains
1-to-2 DMUX which is shown in the task 6 (to see the circuit please refer to task 6). Below is the
Decoder:
DECODER_1
1
0
A0
1
0
EN
0
Y0
1
Y1
The truth table used to verify the out puts is given below:
Task 8: Build and Test a 2-to-4 Decoder Using NOR/NOR Logic
In this task we have to build 1-bit, 2-to-4 using only NOR/NOR logic. The decoder shown below
uses a NOR/NOR since from the beginning of this experiment we are following the NOR/NOR
logic. There for we will have the 1-bit, 2-to-4 decoder based on the NOR/NOR logic.
The 1-bit 2-to-4 decoder using NOR/NOR logic is shown below:
DECODER_1
DECODER_1
A1
A0
Y0
EN
EN
Y1
A0
Y0
EN
Y1
Y0
Y1
DECODER_1
A0
Y0
Y2
EN
Y1
Y3
A0
The imbedded version of the 1-bit 2-to-4 decoder is shown below
0
DECODER_2
1
0
A1
1
0
A0
1
0
0
Y0
Y1
Y2
Y3
EN
0
1
Truth Table Used to verify the outputs is given below:
Task 9: Design, Build and Test a 4-to-16 Decoder Using 2-to-4 Decoders
In this task we have to design a 4-to-16 decoder using only the 2-to-4 decoder subcircuits I
constructed in the task 8. Then I have to imbed the circuit and save it in MyLibrary. The 4-to-16
decoder build by using 2-to-4 decoder is shown below:0
DECODER_2
A1
Y00
Y0
DECODER_2
A1
Y0
1
0
A0
Y2
0
A0
Y02
Y2
Y1
A0
0
Y01
Y1
A1
0
Y03
Y3
EN
1
0
Y3
EN
EN
0
DECODER_2
1
0
A1
1
Y0
Y04
Y1
Y05
0
A0
Y2
Y06
0
Y07
Y3
EN
1
0
A3
0
DECODER_2
0
A1
Y08
Y0
A2
0
Y09
Y1
1
0
A0
Y10
Y2
0
Y11
Y3
EN
0
DECODER_2
0
A1
Y0
Y1
A0
Y12
Y13
Y2
Y14
Y3
Y15
0
EN
0
I used a table to test 4-to-16 decoder, the table that I used is shown below:
Subcircuit of the 4-to-16 decoder is given below:
DECODER_4
A3
A2
A1
A0
EN
Y00
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
CONCLUSION: - This is so far the longest lab that I have done so far, I had to sit countless hours to
just finish this report. I learnt a lot of stuff from this simulation lab, I learnt how to use the
NOR/NOR gates instead of AND gates. I also leant that why do we need Multiplexers and Decoders,
and what is the difference between them. But I hope after this lab I don’t have a lab as long as this
one.