ELEC692n VLSI Signal Processing Architecture
assignment #1
(due date Oct. 8)
1. For the DFG shown in Fig. 1, compute the iteration bound of this DFG using the
LPM algorithm. (Assume that the addition and multiplication require 1and 2 unit
time, respectively).
IN
A1
M1
+
X
A2
+
A5
M2
+
X
A4
+
A6
+
M3
A3
D
X
M4
+
D
X
M5
X
+
+
A7
A8
OUT
Fig. 1 The lattice filter
2. Consider the IIR digital filter block diagram shown in Fig2. Assume that the
multiplication operation takes 2 u.t. and the addition operation takes 1 u.t.
a) Calculate the critical path for the IIR filter.
b) Pipeline the IIR filter by placing latches at appropriate feed-forward cutsets
to reduce the critical path to 3 u.t.
x(n)
A2
+
M2
+
A1
+
M3
X
X
M1
D
D
M4
Fig. 2 The digital IIR filter
X
X
+
+
A3
A4
3. Consider a direct-form implementation of the FIR filter
y ( n)ax ( n)bx ( n2)cx( n3)
Assume that the time required for 1 multiply-add operation is T.
a) Pipeline this filter such that the clock period is approximately T.
b) Draw a block filter architecture for a block size of three. Pipeline this block
filter such that the clock period is about T. What is the system sample rate?
c) Pipeline the block filter in part (b) such that the clock period is about T/2.
Show the appropriate cutsets and label the outputs clearly. What is the system
rate now?
4. Two implementation of an 8-tap FIR filter are shown in Fig. 3. Assume the critical
path (or the propagation delay) of a multiplier to be twice that of an adder, i.e.
TM
 2T a . Therefore, the charging capacitance of a multiplier is twice that of
an adder. Further assume that the total capacitance of a multiplier is 10 times that
of an adder, i.e., C m
 10Ca . The critical path of the direct-form structure in Fig.
3(a) is T M  7T a  9T a . The structure in Fig. 3(b) can be operated with a
lower supply voltage to meet the clock period or sampling period constraint of
9T a . Thus, the structure in Fig. 3(b) can be used to reduce the power
consumption. Assume that the structure in Fig. 3(a) is operated with a supply
voltage of 4 V. Assume the technology threshold voltage to 0.5V. The supply
voltage must be greater than 1.2 V to achieve the acceptable noise margin.
What is the minimum supply voltage at which the structure shown in Fig. 3(b)
can be operated to achieve the desired sampling period of 9T a ? Calculate the
percentage of reduction in power consumption for the structure in Fig. 3(b) as
compared with that in Fig. 3(a). Neglect the propagation delay and capacitance of
delay elements in calculation of critical path or power consumption.
x(n)
D
X
a0
D
X
a1
D
X
a2
+
(a)
D
X
a3
+
D
X
a4
+
D
+
X
D
X
a6
a5
+
X
a7
+
+
x(n)
D
X
a0
D
X
X
X
a1
a2
+
y(n)
D
D
X
X
a3
a4
+
+
D
X
a6
a5
+
+
+
D
X
+
D
(b)
Fig. 3 The implementations of an 8-tap FIR filter
5. Consider the wave digital filter shown in Fig. 4. Assume that each multiply
operation requires 20 nsec and each add operation requires 8 nsec.
a) Calculate the iteration period bound of this filter by inspection.
b) What is the critical path?
c) Manually pipeline and/or retime this filter to achieve a critical path equal to
the iteration period bound.
x(n)
+
D
D
+
+
X
+
+
y(n)
+
X
2D
+
+
2D
Fig. 4 The wave digital filter structure
6. For the DFG in Fig. 5, find the retimed DFG for r(1)=0, r(2)=0, r(3)=-1, r(4)=-2,
r(5)=-1, r(6)=0, r(7)=0 and r(8)=0.
1
+
+
D
b
2D
X
D a
2
+
3
X
c
4
2D
X
+
5
7
8
d
X
6
Fig. 5 The biquad filter
7. Consider the N-stage normalized lattice filter in Fig. 6. Let N=25, i.e. the filter has
25 modules, and assume that addition and multiplication take 1 and 2 u.t.,
respectively.
a) Compute the critical path and the minimum clock period for this filter.
b) Using a 2-slow transformation, retime the filter so that it is pipelined at the
module level, i.e., each wire between modules has at least one delay. What is
the clock period and sample period of the retimed filter?
OUT
IN
X
Module
N
D
Module
N-1
Module
2
D
D
MODULE
+
X
X
X
+
+
X
X
Fig. 6 The N-stage normalized lattice filter
Module
1
D