ECE 448
Lecture 4
Structural Design Style
Behavioral Design Style:
Registers and Counters
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Required reading
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 6, Combinational-Circuit Building
Blocks (sections 6.6.5-6.6.7 optional)
Chapter 5.5, Design of Arithmetic Circuits
Using CAD Tools
Chapter 7, Flip-Flops, Registers, Counters,
and a Simple Processor
(7.14 optional)
ECE 448 – FPGA and ASIC Design with VHDL
2
Optional Reading
• Sundar Rajan, Essential VHDL: RTL Synthesis
Done Right
Chapter 3, Gates, Decoders and Encoders
Chapter 4, Registers and Latches
(see errata at http://www.vahana.com/bugs.htm)
ECE 448 – FPGA and ASIC Design with VHDL
3
Register Transfer Level (RTL) Design Description
Combinational
Logic
Combinational
Logic
…
Registers
ECE 448 – FPGA and ASIC Design with VHDL
4
Structural
Design Style
ECE 448 – FPGA and ASIC Design with VHDL
5
VHDL Design Styles
VHDL Design
Styles
dataflow
Concurrent
statements
structural
Components and
interconnects
ECE 448 – FPGA and ASIC Design with VHDL
behavioral
Sequential statements
• Registers & counters
6
Structural VHDL
Major instructions
• component instantiation (port map)
• generate scheme for component instantiations
(for-generate)
• component instantiation with generic
(generic map, port map)
ECE 448 – FPGA and ASIC Design with VHDL
7
Structural VHDL
Major instructions
• component instantiation (port map)
• generate scheme for component instantiations
(for-generate)
• component instantiation with generic
(generic map, port map)
ECE 448 – FPGA and ASIC Design with VHDL
8
Circuit built of medium scale components
s(0)
r(0)
0
r(1)
1
p(0)
p(1)
r(2)
p(2)
r(3)
w0
w1
0
r(5)
1
p(3)
q(1)
y1
w2
w3
r(4)
y0
q(0)
z
priority
ena
w
0
w
1
En
y
0
y
1
y
2
y
3
z(0)
z(1)
z(2)
z(3)
dec2to4
s(1)
ECE 448 – FPGA and ASIC Design with VHDL
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2-to-1 Multiplexer
s
w
0
0
w
1
1
f
(a) Graphical symbol
ECE 448 – FPGA and ASIC Design with VHDL
s
f
0
w
0
1
w
1
(b) Truth table
10
VHDL code for a 2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
PORT ( w0, w1, s
f
END mux2to1 ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
11
Priority Encoder
w0
y0
w1
y1
w2
z
w3
w3 w2 w1 w0
0
0
0
0
1
0
0
0
1
x
ECE 448 – FPGA and ASIC Design with VHDL
0
0
1
x
x
0
1
x
x
x
y1 y0
z
d
0
0
1
1
0
1
1
1
1
d
0
1
0
1
12
VHDL code for a Priority Encoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN
y : OUT
z : OUT
END priority ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE dataflow OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
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2-to-4 Decoder
En w w
1 0
y y y y
0 1 2 3
1
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
1
0
x
x
0
0
0
0
(a) Truth table
ECE 448 – FPGA and ASIC Design with VHDL
w
0
w
1
En
y
0
y
1
y
2
y
3
(b) Graphical
symbol
14
VHDL code for a 2-to-4 Decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN
En : IN
y
: OUT
END dec2to4 ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(0 TO 3) ) ;
ARCHITECTURE dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
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Circuit built of medium scale components
s(0)
r(0)
0
r(1)
1
p(0)
p(1)
r(2)
p(2)
r(3)
w0
w1
0
r(5)
1
p(3)
q(1)
y1
w2
w3
r(4)
y0
q(0)
z
priority
ena
w
0
w
1
En
y
0
y
1
y
2
y
3
z(0)
z(1)
z(2)
z(3)
dec2to4
s(1)
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16
Structural description – example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority_resolver IS
PORT (r
: IN
STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s
: IN
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;
ARCHITECTURE structural OF priority_resolver IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;
ECE 448 – FPGA and ASIC Design with VHDL
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Structural description – example (2)
COMPONENT mux2to1
PORT (w0, w1, s
f
END COMPONENT ;
: IN
: OUT
COMPONENT priority
PORT (w
: IN
y
: OUT
z
: OUT
END COMPONENT ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
COMPONENT dec2to4
PORT (w
: IN
En
: IN
y
: OUT
END COMPONENT ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(0 TO 3) ) ;
ECE 448 – FPGA and ASIC Design with VHDL
STD_LOGIC ;
STD_LOGIC ) ;
18
Structural description – example (3)
BEGIN
u1: mux2to1 PORT MAP (w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(1) <= r(3);
u2: mux2to1 PORT MAP (w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));
u3: priority PORT MAP (w => p,
y => q,
z => ena);
u4: dec2to4 PORT MAP (w => q,
En => ena,
y => z);
END structural;
ECE 448 – FPGA and ASIC Design with VHDL
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Named association connectivity
• recommended in majority of cases,
prevents ommisions and mistakes
COMPONENT dec2to4
PORT (w
: IN
En
: IN
y
: OUT
END COMPONENT ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(0 TO 3) ) ;
u4: dec2to4 PORT MAP (w => q,
En => ena,
y => z);
ECE 448 – FPGA and ASIC Design with VHDL
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Positional association connectivity
• allowed, especially for the cases of
• small number of ports
• multiple instantiations of the same component,
in regular structures
COMPONENT dec2to4
PORT (w
: IN
En
: IN
y
: OUT
END COMPONENT ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(0 TO 3) ) ;
u4: dec2to4 PORT MAP (w, En, y);
ECE 448 – FPGA and ASIC Design with VHDL
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Structural description with
positional association connectivity
BEGIN
u1: mux2to1 PORT MAP (r(0), r(1), s(0), p(0));
p(1) <= r(2);
p(1) <= r(3);
u2: mux2to1 PORT MAP (r(4) , r(5), s(1), p(3));
u3: priority PORT MAP (p, q, ena);
u4: dec2to4 PORT MAP (q, ena, z);
END structural;
ECE 448 – FPGA and ASIC Design with VHDL
22
Packages
ECE 448 – FPGA and ASIC Design with VHDL
23
Package – example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE GatesPkg IS
COMPONENT mux2to1
PORT (w0, w1, s : IN
f
: OUT
END COMPONENT ;
STD_LOGIC ;
STD_LOGIC ) ;
COMPONENT priority
PORT (w : IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y
: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z
: OUT STD_LOGIC ) ;
END COMPONENT ;
ECE 448 – FPGA and ASIC Design with VHDL
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Package – example (2)
COMPONENT dec2to4
PORT (w : IN
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En
: IN
STD_LOGIC ;
y
: OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END COMPONENT ;
constant ADDAB : std_logic_vector(3 downto 0) := "0000";
constant ADDAM : std_logic_vector(3 downto 0) := "0001";
constant SUBAB : std_logic_vector(3 downto 0) := "0010";
constant SUBAM : std_logic_vector(3 downto 0) := "0011";
constant NOTA : std_logic_vector(3 downto 0) := "0100";
constant NOTB : std_logic_vector(3 downto 0) := "0101";
constant NOTM : std_logic_vector(3 downto 0) := "0110";
constant ANDAB : std_logic_vector(3 downto 0) := "0111";
END GatesPkg;
ECE 448 – FPGA and ASIC Design with VHDL
25
Package usage (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.GatesPkg.all;
ENTITY priority_resolver IS
PORT (r
: IN
STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s
: IN
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;
ARCHITECTURE structural OF priority_resolver IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;
ECE 448 – FPGA and ASIC Design with VHDL
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Package usage (2)
BEGIN
u1: mux2to1 PORT MAP (w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(1) <= r(3);
u2: mux2to1 PORT MAP (w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));
u3: priority PORT MAP (w => p,
y => q,
z => ena);
u4: dec2to4 PORT MAP (w => q,
En => ena,
y => z);
END structural;
ECE 448 – FPGA and ASIC Design with VHDL
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Component
Configuration
ECE 448 – FPGA and ASIC Design with VHDL
28
Configuration declaration
CONFIGURATION SimpleCfg OF priority_resolver IS
FOR structural
FOR ALL: mux2to1
USE ENTITY work.mux2to1(dataflow);
END FOR;
FOR u3: priority
USE ENTITY work.priority(dataflow);
END FOR;
FOR u4: dec2to4
USE ENTITY work.dec2to4(dataflow);
END FOR;
END FOR;
END SimpleCfg;
ECE 448 – FPGA and ASIC Design with VHDL
29
Configuration specification
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.GatesPkg.all;
ENTITY priority_resolver IS
PORT (r
: IN
s
: IN
z
: OUT
END priority_resolver;
STD_LOGIC_VECTOR(5 DOWNTO 0) ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
ARCHITECTURE structural OF priority_resolver IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;
FOR ALL: mux2to1 USE ENTITY work.mux2to1(dataflow);
FOR u3: priority USE ENTITY work.priority(dataflow);
FOR u4: dec2to4 USE ENTITY work.dec2to4(dataflow);
ECE 448 – FPGA and ASIC Design with VHDL
30
Generate scheme
for components
ECE 448 – FPGA and ASIC Design with VHDL
31
Structural VHDL
Major instructions
• component instantiation (port map)
• generate scheme for component instantiations
(for-generate)
• component instantiation with generic
(generic map, port map)
ECE 448 – FPGA and ASIC Design with VHDL
32
Example 1
s0
s1
w0
w3
w4
s2
s3
w7
f
w8
w11
w12
w15
ECE 448 – FPGA and ASIC Design with VHDL
33
A 4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT (
w0, w1, w2, w3
s
: IN
f
: OUT
END mux4to1 ;
: IN
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
ARCHITECTURE Dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END Dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
34
Straightforward code for Example 1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Example1 IS
PORT ( w
: IN
s
: IN
f
: OUT
END Example1 ;
STD_LOGIC_VECTOR(0 TO 15) ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ) ;
ECE 448 – FPGA and ASIC Design with VHDL
35
Straightforward code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3
s
f
END COMPONENT ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
Mux1: mux4to1 PORT MAP ( w(0),
Mux2: mux4to1 PORT MAP ( w(4),
Mux3: mux4to1 PORT MAP ( w(8),
Mux4: mux4to1 PORT MAP ( w(12),
Mux5: mux4to1 PORT MAP ( m(0),
END Structure ;
w(1),
w(5),
w(9),
w(13),
m(1),
ECE 448 – FPGA and ASIC Design with VHDL
w(2),
w(6),
w(10),
w(14),
m(2),
w(3),
w(7),
w(11),
w(15),
m(3),
s(1 DOWNTO 0), m(0) ) ;
s(1 DOWNTO 0), m(1) ) ;
s(1 DOWNTO 0), m(2) ) ;
s(1 DOWNTO 0), m(3) ) ;
s(3 DOWNTO 2), f ) ;
36
Modified code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3
s
f
END COMPONENT ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ;
STD_LOGIC ) ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;
END GENERATE ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
ECE 448 – FPGA and ASIC Design with VHDL
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Structural VHDL
Major instructions
• component instantiation (port map)
• generate scheme for component instantiations
(for-generate)
• component instantiation with generic
(generic map, port map)
ECE 448 – FPGA and ASIC Design with VHDL
38
Variable rotator - Interface
A
16
4
B
A <<< B
16
C
ECE 448 – FPGA and ASIC Design with VHDL
39
Block diagram
ECE 448 – FPGA and ASIC Design with VHDL
40
VHDL code for a 16-bit
2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1_16 IS
PORT ( w0
w1
s
f
END mux2to1_16 ;
: IN
: IN
: IN
: OUT
STD_LOGIC_VECTOR(15 DOWNTO 0);
STD_LOGIC_VECTOR(15 DOWNTO 0);
STD_LOGIC ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
ARCHITECTURE dataflow OF mux2to1_16 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
41
Fixed rotation
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
<<< 3
a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
<<< 5
a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11)
ECE 448 – FPGA and ASIC Design with VHDL
42
VHDL code for
for a fixed 16-bit rotator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fixed_rotator_left_16 IS
GENERIC ( L : INTEGER := 1);
PORT ( a
: IN
STD_LOGIC_VECTOR(15 DOWNTO 0);
y
: OUT
STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END fixed_rotator_left_16 ;
ARCHITECTURE dataflow OF fixed_rotator_left_16 IS
BEGIN
y <= a(15-L downto 0) & a(15 downto 15-L+1);
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL
43
Structural VHDL code for
for a variable 16-bit rotator (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY variable_rotator_16 is
PORT(
A : IN STD_LOGIC_VECTOR(15 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : OUT STD_LOGIC_VECTOR(15 downto 0)
);
END variable_rotator_16;
ECE 448 – FPGA and ASIC Design with VHDL
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Structural VHDL code for
for a variable 16-bit rotator (2)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ARCHITECTURE structural OF variable_rotator_16 IS
COMPONENT mux2to1_16
PORT ( w0
w1
s
f
END COMPONENT ;
: IN
: IN
: IN
: OUT
STD_LOGIC_VECTOR(15 DOWNTO 0);
STD_LOGIC_VECTOR(15 DOWNTO 0);
STD_LOGIC ;
STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
COMPONENT fixed_rotator_left_16
GENERIC ( L : INTEGER := 1);
PORT ( a
: IN
STD_LOGIC_VECTOR(15 DOWNTO 0);
y
: OUT
STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END COMPONENT ;
ECE 448 – FPGA and ASIC Design with VHDL
45
Structural VHDL code for
for a variable 16-bit rotator (3)
TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0);
SIGNAL Al : array1;
SIGNAL Ar : array2;
BEGIN
Al(0) <= A;
G: FOR i IN 0 TO 3 GENERATE
ROT_I: fixed_rotator_left_16
GENERIC MAP (L => 2** i)
PORT MAP ( a => Al(i) ,
y => Ar(i));
MUX_I: mux2to1_16 PORT MAP (w0 => Al(i),
w1 => Ar(i),
s => B(i),
f => Al(i+1));
END GENERATE;
C <= Al(4);
END variable_rotator_16;
ECE 448 – FPGA and ASIC Design with VHDL
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Behavioral Design Style:
Registers & Counters
ECE 448 – FPGA and ASIC Design with VHDL
47
What is a PROCESS?
• A process is a sequence of instructions referred to as
sequential statements.
The keyword PROCESS
• A process can be given a unique name
using an optional LABEL
• This is followed by the keyword
PROCESS
• The keyword BEGIN is used to indicate
the start of the process
• All statements within the process are
executed SEQUENTIALLY. Hence, the
order of statements is important.
testing: PROCESS
BEGIN
test_vector<=“00”;
WAIT FOR 10 ns;
test_vector<=“01”;
WAIT FOR 10 ns;
test_vector<=“10”;
WAIT FOR 10 ns;
test_vector<=“11”;
WAIT FOR 10 ns;
END PROCESS;
• A process must end with the keywords
END PROCESS.
ECE 448 – FPGA and ASIC Design with VHDL
48
Anatomy of a Process
OPTIONAL
[label:] PROCESS [(sensitivity list)]
[declaration part]
BEGIN
statement part
END PROCESS [label];
ECE 448 – FPGA and ASIC Design with VHDL
49
Statement Part
• Contains Sequential Statements to be
Executed Each Time the Process Is
Activated
• Analogous to Conventional Programming
Languages
ECE 448 – FPGA and ASIC Design with VHDL
50
PROCESS with a SENSITIVITY LIST
• List of signals to which the
process is sensitive.
• Whenever there is an
event on any of the
signals in the sensitivity
list, the process fires.
• Every time the process
fires, it will run in its
entirety.
• WAIT statements are
NOT ALLOWED in a
processes with
SENSITIVITY LIST.
ECE 448 – FPGA and ASIC Design with VHDL
label: process (sensitivity list)
declaration part
begin
statement part
end process;
51
Processes in VHDL
• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful
Statements
• Allow to define an arbitrary behavior that may
be difficult to represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to
Be Synthesized
• Use Processes Freely in Testbenches
ECE 448 – FPGA and ASIC Design with VHDL
52
Use of Processes
in the Synthesizable Code
ECE 448 – FPGA and ASIC Design with VHDL
53
Component Equivalent of a Process
priority: PROCESS (clk)
BEGIN
IF w(3) = '1' THEN
y <= "11" ;
ELSIF w(2) = '1' THEN
y <= "10" ;
ELSIF w(1) = c THEN
y <= a and b;
ELSE
z <= "00" ;
END IF ;
END PROCESS ;
clk
w
a
b
c
y
priority
z
• All signals which appear on the
left of signal assignment
statement (<=) are outputs e.g.
y, z
• All signals which appear on the
right of signal assignment
statement (<=) or in logic
expressions are inputs e.g. w, a,
b, c
• All signals which appear in the
sensitivity list are inputs e.g. clk
• Note that not all inputs need to
be included in the sensitivity list
ECE 448 – FPGA and ASIC Design with VHDL
54
VHDL Design Styles
VHDL Design
Styles
dataflow
Concurrent
statements
structural
Components and
interconnects
behavioral
Sequential statements
Registers & counters
ECE 448 – FPGA and ASIC Design with VHDL
55
Registers
ECE 448 – FPGA and ASIC Design with VHDL
56
D latch
Truth table
Graphical symbol
Clock
0
1
1
Q
D
Clock
D
–
0
1
Q(t+1)
Q(t)
0
1
Timing diagram
t1
t2
t3
t4
Clock
D
Q
Time
ECE 448 – FPGA and ASIC Design with VHDL
57
D flip-flop
Truth table
Graphical symbol
D
Q
Clock
t1
Clk D
 0
 1
0 –
1 –
Timing diagram
t2
t3
Q(t+1)
0
1
Q(t)
Q(t)
t4
Clock
D
Q
Time
ECE 448 – FPGA and ASIC Design with VHDL
58
D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clock : IN
Q
: OUT
END latch ;
D
STD_LOGIC ;
STD_LOGIC) ;
Q
Clock
ARCHITECTURE Behavior OF latch IS
BEGIN
PROCESS ( D, Clock )
BEGIN
IF Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior;
ECE 448 – FPGA and ASIC Design with VHDL
59
D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
D
Q
Clock
ARCHITECTURE Behavior_1 OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior_1 ;
ECE 448 – FPGA and ASIC Design with VHDL
60
D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END flipflop ;
D
Q
Clock
ARCHITECTURE Behavior_2 OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior_2 ;
ECE 448 – FPGA and ASIC Design with VHDL
61
D flip-flop with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock
Q
END flipflop ;
D
: IN
: OUT
STD_LOGIC ;
STD_LOGIC) ;
Q
Clock
Resetn
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
62
D flip-flop with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock
Q
END flipflop ;
: IN
: OUT
STD_LOGIC ;
STD_LOGIC) ;
D
Q
Clock
Resetn
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
63
8-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg8 IS
PORT ( D
Resetn, Clock
Q
END reg8 ;
: IN
STD_LOGIC_VECTOR(7 DOWNTO 0) ;
: IN
STD_LOGIC ;
: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF reg8 IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= "00000000" ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;`
ECE 448 – FPGA and ASIC Design with VHDL
8
8
Resetn
D
Q
Clock
reg8
64
N-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 16 ) ;
PORT ( D
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn, Clock : IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
N
N
Resetn
D
Q
Clock
regn
65
N-bit register with enable
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D
: IN
Enable, Clock : IN
Q
: OUT
END regn ;
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF regn IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1' ) THEN
IF Enable = '1' THEN
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
N
N
Enable
Q
D
Clock
regn
66
Counters
ECE 448 – FPGA and ASIC Design with VHDL
67
2-bit up-counter with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clear, Clock
: IN
Q
: BUFFER
END upcount ;
STD_LOGIC ;
STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
ARCHITECTURE Behavior OF upcount IS
BEGIN
upcount: PROCESS ( Clock )
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF Clear = '1' THEN
Q <= "00" ;
ELSE
Q <= Q + “01” ;
END IF ;
END IF;
END PROCESS;
END Behavior ;
ECE 448 – FPGA and ASIC Design with VHDL
Clear
2
Q
upcount
Clock
68
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clock, Resetn, Enable : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount ;
Enable
4
Q
Clock
upcount
Resetn
ECE 448 – FPGA and ASIC Design with VHDL
69
4-bit up-counter with asynchronous reset (2)
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Count <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF Enable = '1' THEN
Count <= Count + 1 ;
END IF ;
Enable
END IF ;
Q
END PROCESS ;
Q <= Count ;
Clock
END Behavior ;
4
upcount
Resetn
ECE 448 – FPGA and ASIC Design with VHDL
70
Shift Registers
ECE 448 – FPGA and ASIC Design with VHDL
71
Shift register
Sin
D
Q
Q(1)
Q(2)
Q(3)
D
Q
D
Q
Q(0)
D
Q
Clock
Enable
ECE 448 – FPGA and ASIC Design with VHDL
72
Shift Register With Parallel Load
Load
D(3)
D(1)
D(2)
Sin
D
Q
D
D(0)
D
Q
Q
D
Q
Clock
Enable
Q(3)
ECE 448 – FPGA and ASIC Design with VHDL
Q(2)
Q(1)
Q(0)
73
4-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( D
Enable
Load
Sin
Clock
Q
END shift4 ;
: IN
: IN
: IN
: IN
: IN
: BUFFER
4
STD_LOGIC_VECTOR(3 DOWNTO 0) ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
Enable
D
Q
4
Load
Sin
shift4
Clock
ECE 448 – FPGA and ASIC Design with VHDL
74
4-bit shift register with parallel load (2)
ARCHITECTURE Behavior_1 OF shift4 IS
BEGIN
PROCESS (Clock)
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Q(0) <= Q(1) ;
Q(1) <= Q(2);
Q(2) <= Q(3) ;
4
Q(3) <= Sin;
END IF ;
END IF ;
END PROCESS ;
END Behavior_1 ;
Enable
D
Q
4
Load
Sin
shift4
Clock
ECE 448 – FPGA and ASIC Design with VHDL
75
N-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable : IN
STD_LOGIC ;
Load
: IN
STD_LOGIC ;
Sin
: IN
STD_LOGIC ;
Clock
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
N
Enable
D
Q
N
Load
Sin
shiftn
Clock
ECE 448 – FPGA and ASIC Design with VHDL
76
N-bit shift register with parallel load (2)
ARCHITECTURE Behavior OF shiftn IS
BEGIN
PROCESS (Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1' ) THEN
IF Load = '1' THEN
Q <= D ;
ELSIF Enable = ‘1’ THEN
Genbits: FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i+1) ;
END LOOP ;
Q(N-1) <= Sin ;
N
Enable
END IF;
D
Q
END IF ;
END PROCESS ;
Load
END Behavior ;
Sin
N
shiftn
Clock
ECE 448 – FPGA and ASIC Design with VHDL
77