4/17/2020
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Announcements/reminders
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Exam 2: next Wednesday
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Once again, allowed 1 8.5” x 11” sheet of notes
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I’ll provide you with a list of instructions—will post to the web page shortly
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Practice problems to be posted today
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Lecture outline
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Review: microprocessor interfaces
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More on 80386 interfaces
2 Microprocessors I: Lecture 25

DMA interface
Interrupt interface
Review: 80386 Interfaces (Fig
9.3, p. 376)
Coprocessor interface
HOLD
HLDA
INTR
NMI
RESET
PEREQ
BUSY
ERROR
A
2
-A
31
BE
0
-BE
3
D
0
-D
31
W/R
D/C
M/IO
ADS
READY
NA
LOCK
BS16
Memory/
IO interface
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LOCK: used in multiprocessor systems

One processor must claim bus control to execute transaction

BS
16
: Change buses to 16-bit mode
4 4/17/2020 Microprocessors I: Lecture 25

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Signals:
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INTR: interrupt
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NMI: Nonmaskable interrupt request
RESET: system reset

Interrupt request/interrupt-acknowledge signal handshake

IF can disable INTR; NMI cannot be disabled

RESET: initialize internal registers, execute reset service routine
5 Microprocessors I: Lecture 25

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DMA
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Two signals: HOLD and HLDA


HOLD: bus hold request by DMA controller
80386DX goes into hold state, its bus signals are in high-impedance state

HLDA: acknowledge from 80386DX to give up control of bus
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Coprocessor Interface
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PEREQ: coprocessor request for data transfer

BUSY: coprocessor busy; no new calculation

ERROR: coprocessor error occurred
Microprocessors I: Lecture 25 6

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

Used to synchronize both internal and external operations
Generated by external oscillator
Specified in terms of frequency or cycle time


Cycle time = 1 / frequency
E.g. 20 MHz clock  cycle time = 1 / 20x10 6 = 50 ns
80386 specifics




External pin CLK2: clock input
Internal clock: ½ frequency of CLK2
Valid internal frequencies for different 80386 models: 16, 20, 25, 33 MHz
One (internal) cycle: 1 “T state”
7 Microprocessors I: Lecture 25

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Activity performed when accessing information in memory or I/O devices
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Nonpipelined vs pipelined
Nonpipelined bus cycle (Figure
9.10)



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T1 : outputs the address on address bus, a bus cycle indication code, control signal
T2: external device accept data, or provide data to data bus address is still available on address bus while data transfer
Each bus cycle has two T states (=
4 CLK2 cycles = 100ns for 20MHz
80386)
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Pipelining : Addressing for the next busy cycle is overlapped with data transfer of prior bus cycle (Fig 9.11)

Address, bus cycle indication code and control signals are output in T2 of the prior cycle, instead of the T1 that follows
Compare Figure 9.10 with 9.11
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
Fig. 9.11: Address n becomes valid in T2 of prior bus cycle
Fig. 9.11: while data transfer n occurs, address n+1 is output on address bus
80386 begins accessing the next storage location while it is still performing read/write of data for the previous location
Address-access time : amount of time that address is stable prior to read/write of data

Pipelined mode has longer effective address-access time


Given fixed address-access time (equal speed memory design), pipelined bus cycle will have a shorter duration than nonpipelined busy cycle
I.e. pipelined bus can operate at a higher clock rate than nonpipelined bus cycle.
Microprocessors I: Lecture 25 9

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Idle state
 no need to access memory

Next bus cycle is not initiated immediately
Wait state (Tw)
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Request by an event in external hardware
READY signal (input signal) sampled in the later part of
T2
As long as READY is 1, read/write data transfer does not take place and T2 becomes Tw

Bus cycle is not completed until READY back to 0
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Nonpipelined Read Cycle Timing (Figure 9.14)

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T
1

1 and T
2
, each has two phases (

1
,

2
) of T
1
:

Address, BE, ADS (signal a valid address is on address bus)
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

1
Bus indication signals (M/IO, D/C, W/R) are made valid of T
2
:
BS16 signal made valid

2

 of T
2
:
READY input is tested


Data is ready on data bus, if READY = 0
Bus cycle extended to Wait state, if READY = 1
11 Microprocessors I: Lecture 25

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Nonpipelined Write Cycle Timing (Figure 9.16)


1 of T
1
:

Address, BE, ADS (signal a valid address is on address bus)




2

Bus indication signals (M/IO, D/C, W/R) are made valid of T
1
:

Outputs the data to be written to memory onto data bus

1
 data made valid until the end of the bus cycle of T
2
:

BS16 signal made valid

2
 of T
2
:
READY input is tested
Wait State

Inserted with READY input signal

Duration of Tw = T
2
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Exam 2 Review
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Look for review slides soon —be prepared with questions on Monday!
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