ECE 448
Lecture 10
Memories: RAM, ROM
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Memory Types
ECE 448 – FPGA and ASIC Design with VHDL
2
Memory Types
Memory
RAM
ROM
Memory
Single port
Dual port
Memory
With asynchronous
read
ECE 448 – FPGA and ASIC Design with VHDL
With synchronous
read
3
FPGA Distributed
Memory
ECE 448 – FPGA and ASIC Design with VHDL
4
CLB Slice
COUT
YB
G4
G3
G2
G1
Y
Look-Up
O
Table
D
Carry
&
Control
Logic
S
Q
CK
EC
R
F5IN
BY
SR
XB
F4
F3
F2
F1
X
Look-Up
Table O
CIN
CLK
CE
ECE 448 – FPGA and ASIC Design with VHDL
Carry
&
Control
Logic
S
D
Q
CK
EC
R
SLICE
5
Xilinx Multipurpose LUT
16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
6
Distributed RAM
RAM16X1S
• A LUT equals 16x1 RAM
• Implements Single and DualPorts
• Cascade LUTs to increase
RAM size
• Synchronous write
• Synchronous/Asynchronous
read
• Accompanying flip-flops used
for synchronous read
ECE 448 – FPGA and ASIC Design with VHDL
=
LUT
• CLB LUT configurable as
Distributed RAM
D
WE
WCLK
A0
A1
A2
A3
O
RAM32X1S
D
WE
WCLK
A0
A1
A2
A3
A4
LUT
=
LUT
or
O
RAM16X2S
D0
D1
WE
WCLK
A0
A1
A2
A3
O0
O1
or
RAM16X1D
D
WE
WCLK
A0
SPO
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
7
FPGA
Block RAM
(BRAM)
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
RAM Blocks in Xilinx FPGAs
RAM blocks
Multipliers
Logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
9
Block RAMs in Xilinx Spartan 3 FPGAs
Port B
Port A
Spartan-3
Dual-Port
Block RAM
Block RAM
• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 104 memory blocks
• 18 kbits = 18,432 bits per block (16 k without parity bits)
• Use multiple blocks for larger memories
• Can be used to build both single-port and true
dual-port RAMs
ECE 448 – FPGA and ASIC Design with VHDL
10
Spartan-3 Block RAM Amounts
ECE 448 – FPGA and ASIC Design with VHDL
11
Block RAM Port Aspect Ratios
1
2
0
4
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
8+1
0
2k x (8+1)
2047
16+2
0
1023
1024 x (16+2)
16,383
ECE 448 – FPGA and ASIC Design with VHDL
12
Block RAM Port Aspect Ratios
ECE 448 – FPGA and ASIC Design with VHDL
13
Single-Port Block RAM
ECE 448 – FPGA and ASIC Design with VHDL
14
Dual-Port Block RAM
ECE 448 – FPGA and ASIC Design with VHDL
15
Dual-Port Bus Flexibility
RAMB4_S16_S8
WEA
Port A In
1K-Bit Depth
ENA
RSTA
DOA[17:0]
Port A Out
18-Bit Width
DOB[8:0]
Port B Out
9-Bit Width
CLKA
ADDRA[9:0]
DIA[17:0]
WEB
ENB
Port B In
2k-Bit Depth
RSTB
CLKB
ADDRB[10:0]
DIB[8:0]
• Each port can be configured with a different data bus
width
• Provides easy data width conversion without any
additional logic
ECE 448 – FPGA and ASIC Design with VHDL
16
Two Independent Single-Port RAMs
RAMB4_S1_S1
Port A In
8K-Bit Depth
0, ADDR[12:0]
WEA
ENA
RSTA
DOA[0]
Port A Out
1-Bit Width
CLKA
ADDRA[12:0]
DIA[0]
Port B In
8K-Bit Depth
1, ADDR[12:0]
WEB
ENB
RSTB
DOB[0]
Port B Out
1-Bit Width
CLKB
ADDRB[12:0]
DIB[0]
•
Added advantage of True DualPort
•
•
No wasted RAM Bits
Can split a Dual-Port 16K RAM into
two Single-Port 8K RAM
•
Simultaneous independent access
to each RAM
ECE 448 – FPGA and ASIC Design with VHDL
• To access the lower RAM
• Tie the MSB address bit to
Logic Low
• To access the upper RAM
• Tie the MSB address bit to
Logic High
17
Inference
vs.
Instantiation
ECE 448 – FPGA and ASIC Design with VHDL
18
ECE 448 – FPGA and ASIC Design with VHDL
19
ECE 448 – FPGA and ASIC Design with VHDL
20
Generic
Inferred
Memories
ECE 448 – FPGA and ASIC Design with VHDL
21
Generic RAM (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------ENTITY ram IS
GENERIC (bits:
INTEGER :=8;
-- # of bits per word
words: INTEGER := 256);
-- # of words in the memory
PORT (
addr:
data_in:
wr_ena:
clk:
data_out:
IN INTEGER RANGE 0 to words-1;
IN STD_LOGIC_VECTOR(bits -1 downto 0);
IN STD_LOGIC;
IN STD_LOGIC;
OUT STD_LOGIC_VECTOR(bits – 1 downto 0)
);
END ram;
ECE 448 – FPGA and ASIC Design with VHDL
22
Single-port RAM with asynchronous read (2)
ARCHITECTURE async_read_ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits – 1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
data_out <= memory(addr);
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
IF(wr_ena=‘1’) THEN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
END async_read_RAM;
ECE 448 – FPGA and ASIC Design with VHDL
23
Report from Synthesis (1)
Mapping to part: xc3s50vq100-5
Cell usage:
MUXF5
8 uses
RAM64X1S
32 uses
LUT3
20 uses
RAM/ROM usage summary
Single Port Rams (RAM64X1S):
32
Mapping Summary:
Total LUTs: 148 (9%)
ECE 448 – FPGA and ASIC Design with VHDL
24
Report from Implementation (1)
Target Device : xc3s50
Target Package : vq100
Target Speed : -5
Design Summary
-------------Logic Utilization:
Number of 4 input LUTs:
20 out of 1,536 1%
Logic Distribution:
Number of occupied Slices:
74 out of 768 9%
Number of Slices containing only related logic:
74 out of
74 100%
Number of Slices containing unrelated logic:
0 out of
74 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:
148 out of 1,536 9%
Number used as logic:
20
Number used for 32x1 RAMs:
128
(Two LUTs used per 32x1 RAM)
ECE 448 – FPGA and ASIC Design with VHDL
25
Single-port RAM with synchronous read (2)
ARCHITECTURE sync_read_ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
IF(wr_ena=‘1’) THEN
memory(addr) <= data_in;
ELSE
data_out <= memory(addr);
END IF;
END IF;
END PROCESS;
END sync_read_RAM;
ECE 448 – FPGA and ASIC Design with VHDL
26
Report from Synthesis (2)
Mapping to part: xc3s50pq208-5
Cell usage:
GND
1 use
RAMB16_S9
1 use
VCC
1 use
RAM/ROM usage summary
Block Rams :
1 of 4 (25%)
Mapping Summary:
Total LUTs: 0 (0%)
ECE 448 – FPGA and ASIC Design with VHDL
27
Report from Implementation (2)
Target Device : xc3s50
Target Package : pq208
Target Speed : -5
Design Summary
-------------Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic:
0 out of
0 0%
Number of Slices containing unrelated logic:
0 out of
0 0%
*See NOTES below for an explanation of the effects of unrelated logic
Number of bonded IOBs:
26 out of 124 20%
Number of Block RAMs:
1 out of
4 25%
Number of GCLKs:
1 out of
8 12%
ECE 448 – FPGA and ASIC Design with VHDL
28
Generic ROM (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------ENTITY rom IS
GENERIC (bits:
INTEGER:=8;
-- # of bits per word
words: INTEGER := 8);
-- # of words in the memory
PORT ( addr:
data_out:
);
END rom;
IN INTEGER RANGE 0 TO words-1;
OUT STD_LOGIC_VECTOR(bits – 1 DOWNTO 0)
ECE 448 – FPGA and ASIC Design with VHDL
29
Generic ROM (2)
ARCHITECTURE behavioral OF rom IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits – 1 DOWNTO 0);
CONSTANT memory: vector_array :=
("0000_0000",
"0000_0010",
"0000_0100",
"0000_1000",
"0001_0000",
"0010_0000",
"0100_0000",
"1000_0000");
BEGIN
data_out <= memory(addr);
END rom;
ECE 448 – FPGA and ASIC Design with VHDL
30
Generic ROM (3) – hexadecimal notation
ARCHITECTURE behavioral OF rom IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits – 1 DOWNTO 0);
CONSTANT memory: vector_array :=
(X"00",
X"02",
X"04",
X"08",
X"10",
X"20",
X"40",
X"80");
BEGIN
data_out <= memory(addr);
END rom;
ECE 448 – FPGA and ASIC Design with VHDL
31
std_logic vs. std_ulogic
TYPE std_ulogic IS
(‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
SUBTYPE std_logic IS std_ulogic
RANGE ‘X’ TO ‘-’;
ECE 448 – FPGA and ASIC Design with VHDL
32
Conversion std_logic_vector => integer (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity test is
end test;
architecture behavior of test is
SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL u_addr: UNSIGNED(7 DOWNTO 0);
SIGNAL i_addr : INTEGER;
begin
u_addr <= unsigned(stdl_addr);
i_addr <= conv_integer(u_addr);
end behavior;
ECE 448 – FPGA and ASIC Design with VHDL
33
Conversion std_logic_vector => integer (2)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity test is
end test;
architecture behavior of test is
SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL i_addr : INTEGER;
begin
u_addr <= conv_integer(unsigned(stdl_addr));
end behavior;
ECE 448 – FPGA and ASIC Design with VHDL
34
Instruction ROM example (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY instruction_rom IS
GENERIC ( w : INTEGER := 16;
n : INTEGER := 8;
m : INTEGER := 3);
PORT (
Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0)
);
END instruction_rom;
ECE 448 – FPGA and ASIC Design with VHDL
35
Instruction ROM example (2)
ARCHITECTURE ins_rom OF insstruction_rom IS
SIGNAL temp: INTEGER RANGE 0 TO 7;
TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0);
CONSTANT memory : vector_array :=
(
"0000_0000_0000_0000",
"0000_0000_0000_0000",
"1101_0100_0101_1001",
"1101_0100_0101_1000",
"0110_1000_1000_0111",
"0100_1001_1001_1010",
"1111_0110_0111_0101",
"1111_0110_0111_0100",
BEGIN
temp <= conv_integer(unsigned(Instr_addr));
Instr <= memory(temp);
END instruction_rom;
ECE 448 – FPGA and ASIC Design with VHDL
36
Generic dual-port memory with
asynchronous output (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dual_port_RAM IS
PORT(
wen :
IN STD_LOGIC;
clk :
IN STD_LOGIC;
data_in :
IN STD_LOGIC_VECTOR(31 DOWNTO 0);
addr1 :
IN STD_LOGIC_VECTOR(4 DOWNTO 0);
addr2 :
IN STD_LOGIC_VECTOR (4 DOWNTO 0);
data_out1:
OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_out2:
OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dual_port_RAM;
ECE 448 – FPGA and ASIC Design with VHDL
37
Generic dual-port memory with
asynchronous output (2)
ARCHITECTURE async_read_RAM OF dual_port_RAM IS
TYPE vector_array IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL memory : vector_array;
SIGNAL temp1: INTEGER RANGE 0 TO 31;
SIGNAL temp2: INTEGER RANGE 0 TO 31;
BEGIN
temp1 <= conv_integer(unsigned(addr1));
temp2 <= conv_integer(unsigned(addr2));
data_out1 <= memory(temp1);
data_out2 <= memory(temp2);
PROCESS(clk)
BEGIN
IF (rising_edge(clk)) THEN
IF (wen = '1') THEN
memory(temp2) <= data_in;
END IF;
END IF;
END PROCESS;
END async_read_RAM;
ECE 448 – FPGA and ASIC Design with VHDL
38
Report from Implementation
Target Device : xc3s50
Target Package : pq208
Target Speed : -5
Design Summary
-------------Logic Utilization:
Number of 4 input LUTs:
66 out of 1,536 4%
Logic Distribution:
Number of occupied Slices:
97 out of 768 12%
Number of Slices containing only related logic:
97 out of
97 100%
Number of Slices containing unrelated logic:
0 out of
97 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:
194 out of 1,536 12%
Number used as logic:
66
Number used for Dual Port RAMs:
128
(Two LUTs used per Dual Port RAM)
ECE 448 – FPGA and ASIC Design with VHDL
39
Specification of memory types recognized
by Synplify Pro
SIGNAL memory : vector_array;
Block RAM Memory:
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is "block_ram";
LUT-based Distributed Memory:
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is “select_ram";
ECE 448 – FPGA and ASIC Design with VHDL
40
FPGA
specific memories
ECE 448 – FPGA and ASIC Design with VHDL
41
RAM 16x1 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity RAM_16X1_DISTRIBUTED is
port(
CLK : in STD_LOGIC;
WE : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_IN : in STD_LOGIC;
DATA_OUT : out STD_LOGIC
);
end RAM_16X1_DISTRIBUTED;
ECE 448 – FPGA and ASIC Design with VHDL
42
RAM 16x1 (2)
architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro, only; ignored during simulation
attribute INIT : string;
attribute INIT of RAM_16x1s_1: label is "0000";
-----------------------------------------------------------------------component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
ECE 448 – FPGA and ASIC Design with VHDL
43
RAM 16x1 (3)
begin
RAM_16x1s_1: ram16x1s generic map (INIT => X”0000")
port map
(O => DATA_OUT,
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DATA_IN,
WCLK => CLK,
WE => WE
);
end RAM_16X1_DISTRIBUTED_STRUCTURAL;
ECE 448 – FPGA and ASIC Design with VHDL
44
RAM 16x8 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity RAM_16X8_DISTRIBUTED is
port(
CLK : in STD_LOGIC;
WE : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
end RAM_16X8_DISTRIBUTED;
ECE 448 – FPGA and ASIC Design with VHDL
45
RAM 16x8 (2)
-- part used by the synthesis tool, Synplify Pro, only; ignored during simulation
attribute INIT : string;
attribute INIT of RAM_16x1_S_1: label is "0000";
component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
ECE 448 – FPGA and ASIC Design with VHDL
46
RAM 16x8 (3)
begin
GENERATE_MEMORY:
for I in 0 to 7 generate
RAM_16x1_S_1: ram16x1s
generic map (INIT => X"0000")
port map
(O => DATA_OUT(I),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DATA_IN(I),
WCLK => CLK,
WE => WE
);
end generate;
end RAM_16X8_DISTRIBUTED_STRUCTURAL;
ECE 448 – FPGA and ASIC Design with VHDL
47
ROM 16x1 (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.all;
entity ROM_16X1_DISTRIBUTED is
port(
ADDR : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : out STD_LOGIC
);
end ROM_16X1_DISTRIBUTED;
ECE 448 – FPGA and ASIC Design with VHDL
48
ROM 16x1 (2)
architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro, only; ignored during simulation
attribute INIT : string;
attribute INIT of rom16x1s_1: label is "F0C1";
component ram16x1s
generic(
INIT : BIT_VECTOR(15 downto 0) := X"0000");
port(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal Low : std_ulogic := ‘0’;
ECE 448 – FPGA and ASIC Design with VHDL
49
ROM 16x1 (3)
begin
rom16x1s_1: ram16x1s
generic map (INIT => X"F0C1")
port map
(O=>DATA_OUT,
A0=>ADDR(0),
A1=>ADDR(1),
A2=>ADDR(2),
A3=>ADDR(3),
D=>Low,
WCLK=>Low,
WE=>Low
);
end ROM_16X1_DISTRIBUTED_STRUCTURAL;
ECE 448 – FPGA and ASIC Design with VHDL
50
Block RAM library components
Component
Data Cells
Depth
Parity Cells
Address Bus
Data Bus
Parity Bus
Width Depth Width
RAMB16_S1
16384
1
-
-
(13:0)
(0:0)
-
RAMB16_S2
8192
2
-
-
(12:0)
(1:0)
-
RAMB16_S4
4096
4
-
-
(11:0)
(3:0)
-
RAMB16_S9
2048
8
2048
1
(10:0)
(7:0)
(0:0)
RAMB16_S18
1024
16
1024
2
(9:0)
(15:0)
(1:0)
RAMB16_S36
512
32
512
4
(8:0)
(31:0)
(3:0)
ECE 448 – FPGA and ASIC Design with VHDL
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Component declaration for BRAM (1)
-- Component Declaration for RAMB16_{S1 | S2 | S4}
-- Should be placed after architecture statement but before begin keyword
component RAMB16_{S1 | S2 | S4}
-- synthesis translate_off
generic (
INIT : bit_vector := X"0";
INIT_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
…………………………………
INIT_3F : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST");
-- synthesis translate_on
port (DO : out STD_LOGIC_VECTOR (0 downto 0)
ADDR : in STD_LOGIC_VECTOR (13 downto 0);
CLK : in STD_ULOGIC;
DI : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
SSR : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
ECE 448 – FPGA and ASIC Design with VHDL
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Genaral template of BRAM instantiation (1)
-- Component Attribute Specification for RAMB16_{S1 | S2 | S4}
-- Should be placed after architecture declaration but before the begin keyword
-- Put attributes, if necessary
-- Component Instantiation for RAMB16_{S1 | S2 | S4}
-- Should be placed in architecture after the begin keyword
RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1
-- synthesis translate_off
generic map (
INIT => bit_value,
INIT_00 => vector_value,
INIT_01 => vector_value,
……………………………..
INIT_3F => vector_value,
SRVAL=> bit_value,
WRITE_MODE => user_WRITE_MODE)
-- synopsys translate_on
port map (DO => user_DO,
ADDR => user_ADDR,
CLK => user_CLK,
DI => user_DI,
EN => user_EN,
SSR => user_SSR,
WE => user_WE);
ECE 448 – FPGA and ASIC Design with VHDL
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Initializing Block RAMs 256x16
INIT_00 : BIT_VECTOR := X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040";
INIT_01 : BIT_VECTOR := X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026";
INIT_02 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
……………………………………………………………………………………………………………………………………
INIT_0F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000")
DATA
ADDRESS
INIT_00
ADDRESS
014A
0F
0C0F
0E
0917
04
006A
03
0068
02
0006
01
0040
00
INIT_01
ADDRESS
0000
1F
0000
1E
014A
14
0C0F
13
03AA
12
0917
11
0026
10
0000
F4
0000
F3
0000
F2
0000
F1
0000
F0
Addresses are
shown in red and
data corresponding
to the same
memory location is
shown in black
INIT_0F
ADDRESS
0000
FF
0000
FE
ECE 448 – FPGA and ASIC Design with VHDL
54
Component declaration for BRAM (2)
VHDL Instantiation Template for RAMB16_S9, S18 and S36
-- Component Declaration for RAMB16_{S9 | S18 | S36}
component RAMB16_{S9 | S18 | S36}
-- synthesis translate_off
generic (
INIT : bit_vector := X"0";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
X"0000000000000000000000000000000000000000000000000000000000000000";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST"; );
-- synthesis translate_on
port (DO : out STD_LOGIC_VECTOR (0 downto 0);
DOP : out STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (13 downto 0);
CLK : in STD_ULOGIC;
DI : in STD_LOGIC_VECTOR (0 downto 0);
DIP : in STD_LOGIC_VECTOR (0 downto 0);
EN : in STD_ULOGIC;
SSR : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
ECE 448 – FPGA and ASIC Design with VHDL
55
Genaral template of BRAM instantiation (2)
-- Component Attribute Specification for RAMB16_{S9 | S18 | S36}
-- Component Instantiation for RAMB16_{S9 | S18 | S36}
-- Should be placed in architecture after the begin keyword
RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1
-- synthesis translate_off
generic map (
INIT => bit_value,
INIT_00 => vector_value,
..........
INIT_3F => vector_value,
INITP_00 => vector_value,
……………
INITP_07 => vector_value
SRVAL => bit_value,
WRITE_MODE => user_WRITE_MODE)
-- synopsys translate_on
port map (DO => user_DO,
DOP => user_DOP,
ADDR => user_ADDR,
CLK => user_CLK,
DI => user_DI,
DIP => user_DIP,
EN => user_EN,
SSR => user_SSR,
WE => user_WE);
ECE 448 – FPGA and ASIC Design with VHDL
56
Block RAM Waveforms – WRITE_FIRST
ECE 448 – FPGA and ASIC Design with VHDL
57
Block RAM Waveforms – READ_FIRST
ECE 448 – FPGA and ASIC Design with VHDL
58
Block RAM Waveforms – NO_CHANGE
ECE 448 – FPGA and ASIC Design with VHDL
59