COMPUTER ORGANIZATION
Unit-II PPT Slides
Text Books: (1) Computer Systems Architecture by M. Morris Mano
(2) Computer Organization by Carl Hamacher
INDEX
UNIT-II PPT SLIDES
Sl. No.
Module as per Session planner
Lecture No
1.
Register Transfer language
L1
2.
Register Transfer Bus and memory transfers
L2
3.
Arithmetic Micro-operations
L3
4.
Logic micro operations
L4
5.
Shift micro operations
L5
6.
Arithmetic logic shift unit
L6
7.
Instruction codes
L7
8.
Computer registers
L8
9.
Computer instructions
L9
10.
Instruction cycle
L10
11.
Memory-Reference Instructions
L11
12.
Input-output and Interrupt
L12
13.
STACK organization
L13
14.
Instruction formats
L14
15.
Addressing modes
L15
16.
DATA Transfer and manipulation
L16
17.
Program control
L17
18.
Reduced Instruction Set Computer
L18
REGISTER TRANSFER LANGUAGE
• Combinational and sequential circuits can be used to create
simple digital systems.
• These are the low-level building blocks of a digital computer.
• Simple digital systems are frequently characterized in terms of
– the registers they contain, and
– the operations that they perform.
• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers
MICROOPERATIONS
• The operations executed on data stored in registers are
called microoperations.
• Examples of microoperations
– Shift
– Load
– Clear
– Increment
– Count
An elementary operation performed (during one clock pulse), on the
information stored in one or more registers.
R  f(R, R)
f: shift, load, clear,
increment, add,
subtract, complement,
and, or, xor, …
Registe
rs
(R)
ALU
(f)
1 clock cycle
INTERNAL HARDWAREORGANIZATION OF A DIGITAL SYSTEM
• Definition of the internal hardware organization of a computer
- Set of registers it contains and their function
- The sequence of microoperations performed on the binary
information stored in the registers
- Control signals that initiate the sequence of microoperations
(to perform the functions)
REGISTER TRANSFER LANGUAGE
The symbolic notation used to describe the microoperation transfers
among registers is called a Register transfer language.
Register transfer language
•A symbolic language
•A convenient tool for describing the internal organization of
digital computers
•Can also be used to facilitate the design process of digital systems.
Register Transfer
• Registers are designated by capital letters, sometimes
followed by numbers (e.g., A, R13, IR).
• Often the names indicate function:
– MAR
– PC
– IR
- memory address register
- program counter
- instruction register
• Information transfer from one register to another is
designated in symbolic form by means of a replacement
operator.
R2  R1
– In this case the contents of register R2 are copied (loaded) into
register R1 and contents of R1 remains same.
Block diagram of a register
7
R1
Register R
15
Numbering of bits
5
4
3
2
1
0
Showing individual bits
0
R2
6
15
8
PC(H)
0
7
PC(L)
Subfields (Divided into two parts)
• Often we want the transfer to occur only under a predetermined
control condition.
if (p=1) then (R2  R1)
where p is a control signal generated in the control section.
• In digital systems, this is often done via a control signal, called a
control function
– If the signal is 1, the action takes place
• This is represented as:
P: R2  R1
Which means “if P = 1, then load the contents of register R1 into
register R2”, i.e., if (P = 1) then (R2  R1)
HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS
Implementation of controlled transfer
P: R2 R1
Block diagram
Control
Circuit
Load
P
R2
Clock
n
R1
t
Timing diagram
t+1
Clock
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function and
the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
SIMULTANEOUS OPERATIONS
• If two or more operations are to occur simultaneously, they
are separated with commas
P: R3  R5, MAR  IR
• Here, if the control function P = 1, load the contents of R5
into R3, and at the same time (clock), load the contents of
register IR into register MAR
BASIC SYMBOLS FOR REGISTER TRANSFERS
Symbols
Capital letters
& numerals
Parentheses ()
Arrow

Colon :
Comma ,
Description
Examples
Denotes a register
MAR, R2
Denotes a part of a register
R2(0-7), R2(L)
Denotes transfer of information
R2  R1
Denotes termination of control function
Separates two micro-operations
P:
A  B, B  A
Bus and Memory Transfers
BUS AND MEMORY TRANSFERS
Bus is a path(of a group of wires) over which information is transferred, from
any of several sources to any of several destinations.
From a register to bus: BUS  R
Register A
Register B
Register C
Register D
Bus lines
Register A
1 2 3 4
Register B
1 2 3 4
B1 C1 D 1
0
4 x1
MUX
Register C
1 2 3 4
B2 C2 D 2
0
4 x1
MUX
Register D
1 2 3 4
B3 C3 D 3
0
x
select
y
4-line bus
4 x1
MUX
B4 C4 D 4
0
4 x1
MUX
Bus and Memory Transfers
TRANSFER FROM BUS TO A DESTINATION REGISTER
Bus lines
Reg. R0
Reg. R1
Reg. R2
D 0 D1 D2 D 3
2x4
Decoder
z
Select
w
Reg. R3
Load
E (enable)
Three-State Bus Buffers
Output Y=A if C=1
High-impedence if C=0
Normal input A
Control input C
Bus line with three-state buffers
Bus line for bit 0
A0
B0
C0
D0
Select
Enable
S0
S1
0
1
2
3
Bus and Memory Transfers
BUS TRANSFER IN RTL
• Depending on whether the bus is to be
mentioned explicitly or not, register transfer can
be indicated as either
R2 R1
or
BUS R1, R2  BUS
• In the former case the bus is implicit, but in the
latter, it is explicitly indicated
Bus and Memory Transfers
MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits containing
some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following
– n data input lines
data input lines
– n data output lines
n
– k address lines
address lines
– A Read control line
k
RAM
– A Write control line
Read
unit
Write
n
data output lines
Bus and Memory Transfers
MEMORY TRANSFER
• Collectively, the memory is viewed at the register level
as a device, M.
• Since it contains multiple locations, we must specify
which address in memory we will be using
• This is done by indexing memory references
• Memory is usually accessed in computer systems by
putting the desired address in a special register, the
Memory Address Register (MAR, or AR)
• When memory is accessed, the contents of the MAR
get sent to the memory unit’s address lines
M
AR
Read
Memory
unit
Data out
Write
Data in
Bus and Memory Transfers
MEMORY READ
• To read a value from a location in memory and load it into a register, the
register transfer language notation looks like this:
R1  M[MAR]
This causes the following to occur
–
–
–
–
The contents of the MAR get sent to the memory address lines
A Read (= 1) gets sent to the memory unit
The contents of the specified address are put on the memory’s output data lines
These get sent over the bus to be loaded into register R1
MEMORY WRITE
• To write a value from a register to a location in memory looks like this in
register transfer language:
M[MAR]  R1
This causes the following to occur
–
–
–
–
The contents of the MAR get sent to the memory address lines
A Write (= 1) gets sent to the memory unit
The values in register R1 get sent over the bus to the data input lines of the memory
The values get loaded into the specified address in the memory
Bus and Memory Transfers
SUMMARY OF REGISTER TRANSFER MICROOPERATIONS
A B
Transfer content of reg. B into reg. A
AR  DR(AD)
Transfer content of AD portion of reg. DR into reg. AR
A  constant
Transfer a binary constant into reg. A
ABUS  R1,
Transfer content of R1 into bus A and, at the same time,
R2  ABUS
AR
DR
M[R]
M
Transfer content of bus A into R2
Address register
Data register
Memory word specified by reg. R
Equivalent to M[AR]
DR  M
M  DR
Memory read operation: transfers content of
memory word specified by AR into DR
Memory write operation: transfers content of
DR into memory word specified by AR
ARITHMETIC MICROOPERATIONS
Computer system microoperations are of four types:
1. Register transfer microoperations transfer binary information from one
register to another
2. Arithmetic microoperations perform arithmetic operations on numeric
data stored in registers.
3. Logic microoperations perform bit manipulation operations on non
numeric data stored in registers.
4. Shift microoperations perform shift operations on data stored in registers.
The basic arithmetic microoperations are
•Addition
•Subtraction
•Increment
•Decrement
The additional arithmetic microoperations are
•Add with carry
•Subtract with borrow
•Transfer/Load
etc. …
ARITHMETIC MICROOPERATIONS
Table: Arithmetic Micro-Operations
R3 
R3 
R2 
R2 
R3 
R1 
R1 
R1 + R2
R1 - R2
R2’
R2’+ 1
R1 + R2’+ 1
R1 + 1
R1 - 1
Contents of R1 plus R2 transferred to R3
Contents of R1 minus R2 transferred to R3
Complement the contents of R2
2's complement the contents of R2 (negate)
subtraction
Increment
Decrement
BINARY ADDER / SUBTRACTOR / INCREMENTER
B3
A3
Binary Adder
C3
FA
C4
B2
A2
C2
FA
S3
B1
A1
C1
FA
S2
B0
A0
C0
FA
S1
S0
Binary Adder-Subtractor
B3
A3
B2
A2
B1
A1
B0
A0
M
C3
FA
C4
Binary Incrementer
S3
S2
A3
y
HA
C4
S
S3
y
HA
S
S2
C0
FA
S0
A1
x
C
C1
FA
S1
A2
x
C
C2
FA
x
y
HA
C
S
S1
A0
1
x
y
HA
C
S
S0
ARITHMETIC CIRCUIT
S1
S0
Cin
A0
X0
S1
S0
0 4x1
1 MUX
2
3
B0
A1
S1
S0
0 4x1
1 MUX
2
3
B1
A2
S1
S0
0 4x1
1 MUX
2
3
B2
A3
S1
S0
0 4x1
1 MUX
2
3
B3
0
S1 S0 Cin
0
0 0
0
0 1
0
1 0
0
1 1
1
0 0
1
0 1
1
1 0
1
1 1
C0
D0
FA
Y0
C1
X1
C1
D1
FA
Y1
C2
X2
C2
D2
FA
Y2
C3
X3
C3
D3
FA
Y3
C4
Cout
1
Y
B
B
B’
B’
0
0
1
1
Output
D=A+B
D=A+B+1
D = A + B’
D = A + B’+ 1
D=A
D=A+1
D=A-1
D=A
Microoperation
Add
Add with carry
Subtract with borrow
Subtract
Transfer A
Increment A
Decrement A
Transfer A
LOGIC MICROOPERATIONS
• It specifies binary operations on the strings of bits stored in registers
– Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
A B F0 F1 F2 … F13 F14 F15
0
0
1
0
1
0
0
0
0
0
0
0
0 … 1
0 … 1
1 … 0
1
1
1
1
1
1
1
1
0
1
0 … 1
0
1
• There are, in principle, 16 different logic functions that can be defined
over two binary input variables
• However, most systems only implement four of these
– AND (), OR (), XOR (), Complement/NOT
• The others can be created from combination of these
Logic Microoperations
LIST OF LOGIC MICROOPERATIONS
• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
- n binary vars →2 2
n
functions
• Truth tables for 16 functions of 2 variables and the corresponding
16 logic micro-operations
x 0011
y 0101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Boolean
Function
F0 = 0
F1 = xy
F2 = xy'
F3 = x
F4 = x'y
F5 = y
F6 = x  y
F7 = x + y
F8 = (x + y)'
F9 = (x  y)'
F10 = y'
F11 = x + y'
F12 = x'
F13 = x' + y
F14 = (xy)'
F15 = 1
MicroName
Operations
F0
Clear
FAB
AND
F  A  B’
FA
Transfer A
F  A’ B
FB
Transfer B
FAB
Exclusive-OR
FAB
OR
F  A  B)’
NOR
F  (A  B)’ Exclusive-NOR
F  B’
Complement B
FAB
F  A’
Complement A
F  A’ B
F  (A  B)’
NAND
F  all 1's
Set to all 1's
HARDWARE IMPLEMENTATION OF LOGIC
MICROOPERATIONS
Ai
Bi
0
1
4X1
MUX
2
3 Select
S1
S0
Function table
S1
0
0
1
1
S0
0
1
0
1
Output
F=AB
F = AB
F=AB
F = A’
-operation
AND
OR
XOR
Complement
Fi
APPLICATIONS OF LOGIC MICROOPERATIONS
• Logic microoperations can be used to manipulate individual
bits or a portions of a word in a register
• Consider the data in a register A. In another register, B, is bit
data that will be used to modify the contents of A
• Selective-set
AA+B
– Selective-complement
AAB
– Selective-clear
A  A • B’
– Mask (Delete)
AA•B
– Clear
AAB
– Insert
A  (A • B) + C
– Compare
AAB
– ...
SELECTIVE SET
• In a selective set operation, the bit pattern in B
is used to set certain bits in A
1100
1010
1110
At
B
At+1
(A  A + B)
• If a bit in B is set to 1, that same position in A
gets set to 1, otherwise that bit in A keeps its
previous value
SELECTIVE COMPLEMENT
• In a selective complement operation, the bit
pattern in B is used to complement certain bits
in A
1100
1010
At
B
0110
At+1
(A  A  B)
• If a bit in B is set to 1, that same position in A
gets complemented from its original value,
otherwise it is unchanged
SELECTIVE CLEAR
• In a selective clear operation, the bit pattern in
B is used to clear certain bits in A
1100
1010
At
B
0100
At+1
(A  A  B’)
• If a bit in B is set to 1, that same position in A
gets set to 0, otherwise it is unchanged
MASK OPERATION
• In a mask operation, the bit pattern in B is
used to clear certain bits in A
1100
1010
At
B
1000
At+1
(A  A  B)
• If a bit in B is set to 0, that same position in A
gets set to 0, otherwise it is unchanged
CLEAR OPERATION
• In a clear operation, if the bits in the same
position in A and B are the same, they are
cleared in A, otherwise they are set in A
1100
1010
At
B
0110
At+1
(A  A  B)
INSERT OPERATION
• An insert operation is used to introduce a specific bit pattern into A
register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired positions
Example
Suppose you wanted to introduce 1010 into the low order four bits of A:
1101 1000 1011 0001
A (Original)
1101 1000 1011 1010
A (Desired)
1101
1111
1101
0000
1000
1111
1000
0000
1011
1111
1011
0000
0001
0000
0000
1010
1101 1000 1011 1010
A (Original)
Mask
A(Intermediate)
Added bits
A (Desired)
SHIFT MICROOPERATIONS
• Shift microoperations are used for serial transfer of data.
• The information transferred through the serial input determines the
type of shift. There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• A right shift operation
Serial
input
• A left shift operation
Serial
input
LOGICAL SHIFT
• In a logical shift the serial input to the shift is a 0.
• A right logical shift operation:
0
• A left logical shift operation:
0
• In a Register Transfer Language, the following notation
is used
– shl
for a logical shift left
– shr
for a logical shift right
– Examples:
• R2  shr R2
• R3  shl R3
CIRCULAR SHIFT
• In a circular shift the serial input is the bit that is shifted
out of the other end of the register.
• A right circular shift operation:
• A left circular shift operation:
• In a RTL, the following notation is used
– cil
for a circular shift left
– cir
for a circular shift right
– Examples:
• R2  cir R2
• R3  cil R3
ARITHMETIC SHIFT
• An arithmetic shift is meant for signed binary numbers
(integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the
multiplication or division
sign
bit
A right arithmetic shift operation:
0
sign
bit
A left arithmetic shift operation:
ARITHMETIC SHIFT
• An left arithmetic shift operation must be
checked for the overflow
0
sign
bit
V
Before the shift, if the leftmost two
bits differ, the shift will result in an
overflow
• In a RTL, the following notation is used
– ashl
for an arithmetic shift left
– ashr
for an arithmetic shift right
– Examples:
• R2  ashr R2
• R3  ashl R3
HARDWARE IMPLEMENTATION OF SHIFT
MICROOPERATIONS
Serial
input (IR)
0 for shift right (down)
Select 1 for shift left (up)
S
0
1
MUX
H0
MUX
H1
MUX
H2
MUX
H3
A0
A1
S
A2
0
1
A3
S
0
1
S
0
1
Serial
input (IL)
ARITHMETIC LOGIC SHIFT UNIT
S3
S2
S1
S0
Ci
Arithmetic D i
Circuit
Select
0
1
2
3
Ci+1
Bi
Ai
Logic
Circuit
S2
0
0
0
0
0
0
0
0
1
1
1
1
0
1
S1 S0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
X
X
X
X
Fi
Ei
shr
shl
Ai-1
Ai+1
S3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4x1
MUX
Cin
0
1
0
1
0
1
0
1
X
X
X
X
X
X
Operation
F=A
F=A+1
F=A+B
F=A+B+1
F = A + B’
F = A + B’+ 1
F=A-1
F=A
F=AB
F = A B
F=AB
F = A’
F = shr A
F = shl A
Function
Transfer A
Increment A
Addition
Add with carry
Subtract with borrow
Subtraction
Decrement A
TransferA
AND
OR
XOR
Complement A
Shift right A into F
Shift left A into F
Instruction Codes
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point
calculations
– Etc.
• However, to understand how processors work, we will start with
a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls
the Basic Computer
THE BASIC COMPUTER
• The Basic Computer has two components, a processor and
memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
RAM
CPU
0
15
0
4095
INSTRUCTIONS
Instruction codes
• Program
– A sequence of (machine) instructions
• (Machine) Instruction- are in the form of binary codes known as
instruction codes.
– A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
• The instructions of a program, along with any needed data are stored
in memory
• Each instruction can be divided into different fields.
- Operation code
- Source/destination Operand
- Source Operand address
- Destination Operand address
- Next Instruction address
• Types of operands
- Addresses, Numbers, characters, logical data
Instruction codes
INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory
to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212) words,
we needs 12 bit to specify which memory address this instruction will
use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long,
that leaves 3 bits for the instruction’s opcode
Instruction Format for immediate
operand
15
12 11
Opcode
0
Address
Addressing
mode
Instruction Format for direct and indirect
address
15 14
12 11
Address
I Opcode
Addressing
mode
0
Instruction codes
ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the
address of the operand), or
– Indirect address: the address in memory of the address in memory
of the data to use
Indirect addressing
Direct addressing
22
0 ADD
457
35
300
457
1 ADD
300
1350
Operand
1350
Operand
+
+
AC
AC
• Effective Address (EA)
– The address, that can be directly used without modification to
access an operand for a computation-type instruction, or as the
target address for a branch-type instruction
Addressing Modes
•
•
•
•
•
•
•
Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
Immediate Addressing
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
Instruction
Opcode
Operand
Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
Instruction
Opcode
Address A
Memory
Operand
Indirect Addressing
• Memory cell pointed to by address field contains the
address of (pointer to) the operand
• EA = (A)
– Look in A, find address (A) and look there for operand
•
e.g. ADD (A)
– Add contents of cell pointed to by contents of A to accumulator
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
– e.g. EA = (((A)))
• Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand
Register Addressing
•
•
•
•
Operand is held in register named in address filed
EA = R
Limited number of registers
Very small address field needed
– Shorter instructions
– Faster instruction fetch
•
•
•
•
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
– Requires good assembly programming or compiler writing
– N.B. C programming
• register int a;
• c.f. Direct addressing
Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand
Register Indirect Addressing
•
•
•
•
•
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand
Displacement Addressing
• EA = A + (R)
• Address field hold two values
– A = base value
– R = register that holds displacement
– or vice versa
Instruction
Opcode Register R
Address A
Memory
Registers
Pointer to Operand
+
Operand
Relative Addressing
•
•
•
•
A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current location pointed to
by PC
• c.f locality of reference & cache usage
Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86
Indexed Addressing
•
•
•
•
A = base
R = displacement
EA = A + (R)
Good for accessing arrays
– EA = A + (R)
– R++
y Combinations
• Postindex
EA = (A) + (R)
• Preindex
EA = (A+(R))
• (Draw the diagrams)
Stack Addressing
• Operand is (implicitly) on top of stack
• e.g.
– ADD Pop top two items from stack and add
Pentium Addressing Modes
• Virtual or effective address is offset into segment
– Starting address plus offset gives linear address
– This goes through page translation if paging enabled
• 12 addressing modes available
–
–
–
–
–
–
–
–
–
Immediate
Register operand
Displacement
Base
Base with displacement
Scaled index with displacement
Base with index and displacement
Base scaled index with displacement
Relative
Instruction codes
PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses,
data, etc
• The processor has a register, the Program Counter (PC) that holds
the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096
locations, the PC only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep track
of what locations in memory it is addressing: The Address Register
(AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The processor
then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the
Accumulator (AC)
PROCESSOR REGISTERS
Instruction codes
• The significance of a general purpose register is that it can be referred
to in instructions
– e.g. load AC with the contents of a specific memory location; store
the contents of AC into a specified memory location
• Often a processor will need a scratch register to store intermediate
results or other temporary data; in the Basic Computer this is the
Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O)
operations
– Input devices are considered to send 8 bits of character data to the
processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input
device
• The Output Register (OUTR) holds an 8 bit character to be send to an
output device
COMPUTER REGISTERS
Registers
Registers in the Basic Computer
11
0
PC
Memory
11
0
4096 x 16
AR
15
0
IR
CPU
15
0
15
TR
7
0
OUTR
0
DR
7
0
15
INPR
0
AC
List of BC Registers
DR or MDR
AR or MAR
AC
IR
PC
TR
INPR
OUTR
16
12
16
16
12
16
8
8
Data Register
Address Register
Accumulator
Instruction Register
Program Counter
Temporary Register
Input Register
Output Register
Holds memory operand
Holds address for memory
Processor register
Holds instruction code
Holds address of instruction
Holds temporary data
Holds the data read from i/p device
Holds the data to be sent to the o/p device
Registers
COMMON BUS SYSTEM
• The registers in the Basic Computer are
connected using a bus
• This gives a savings in circuitry over
complete connections between registers
Registers
COMMON BUS SYSTEM
S2
S1
Bus
S0
Memory unit
4096 x 16
Write
7
Address
Read
AR
1
LD INR CLR
PC
2
LD INR CLR
DR
3
LD INR CLR
E
AC
ALU
4
LD INR CLR
INPR
IR
5
TR
6
LD
LD INR CLR
OUTR
LD
16-bit common bus
Clock
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Register
x
AR
PC
DR
AC
IR
TR
Memory
Registers
COMMON BUS SYSTEM
Read
Memory
4096 x 16
INPR
Write
E
Address
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
ALU
AC
L I
C
L I C
L
I C
L
DR
IR
L I
Register
x
AR
PC
DR
AC
IR
TR
Memory
C
TR
PC
OUTR
AR
LD
L I C
7
1
2
3
4
5
6
16-bit Common Bus
S0 S1 S2
COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register
the bus selects as its input
S2 S1 S0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Register
x
AR
PC
DR
AC
IR
TR
Memory
• Either one of the registers will have its load signal activated,
or the memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus
Registers
Instructions
COMPUTER INSTRUCTIONS
• Basic Computer Instruction Format
Memory-Reference Instructions
15
I
14
12 11
Opcode
0
Address
Register-Reference Instructions
15
0
1
1
12 11
Register operation
1
Input-Output Instructions
15
1 1
12 11
1
1
(OP-code = 000 ~ 110)
(OP-code = 111, I = 0)
0
(OP-code =111, I = 1)
0
I/O operation
Instructions
BASIC COMPUTER INSTRUCTIONS
Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ
Hex Code
I=0
I=1
0xxx 8xxx
1xxx 9xxx
2xxx Axxx
3xxx Bxxx
4xxx Cxxx
5xxx Dxxx
6xxx Exxx
Description
AND memory word to AC
Add memory word to AC
Load AC from memory
Store content of AC into memory
Branch unconditionally
Branch and save return address
Increment and skip if zero
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
7800
7400
7200
7100
7080
7040
7020
7010
7008
7004
7002
7001
Clear AC
Clear E
Complement AC
Complement E
Circulate right AC and E
Circulate left AC and E
Increment AC
Skip next instr. if AC is positive
Skip next instr. if AC is negative
Skip next instr. if AC is zero
Skip next instr. if E is zero
Halt computer
INP
OUT
SKI
SKO
ION
IOF
F800
F400
F200
F100
F080
F040
Input character to AC
Output character from AC
Skip on input flag
Skip on output flag
Interrupt on
Interrupt off
Example Memory reference Instructions
AND
AC  AC X M[AR]
ADD
AC AC + M[AR]
LDA
AC  M[AR]
STA
M[AR]  AC
BUN
PC  AR
BSA
M[AR]  PC, PC  PC+1
ISZ
DR M[AR]
DR  DR+1
M[AR]  DR
If(DR=0) then PC  PC+1
Instructions
INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user
can construct machine language programs to evaluate any
function that is known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
Instruction codes
CONTROL UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations that
implement them
• Control units are implemented in one of two ways
• Hardwired Control
– CU is made up of sequential and combinational circuits to
generate the control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms
that activate the necessary control signals
• We will consider a hardwired implementation of the control unit
for the Basic Computer
Timing and control
TIMING AND CONTROL
Control unit of Basic Computer
15
Instruction register (IR)
14 13 12
11 - 0
Other inputs
3x8
decoder
7 6543 210
D0
I
Combinational
Control
logic
D7
T15
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit
sequence
counter
(SC)
Increment (INR)
Clear (CLR)
Clock
Control
signals
Timing and control
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
T0
Clock
T0
T1
T2
T3
T4
D3
CLR
SC
D3T4: SC 
0
T1
T2
T3
T4
T0
INSTRUCTION CYCLE
•
In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction
•
After an instruction is executed, the cycle starts again at
step 1, for the next instruction
•
Note: Every different processor has its own (different)
instruction cycle
Instruction Cycle
FETCH and DECODE
• Fetch and Decode
T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1
S2
T0
S1
Bus
S0
Memory
unit
7
Address
Read
AR
1
PC
2
LD
INR
IR
LD
Common bus
5
Clock
Instrction Cycle
DETERMINE THE TYPE OF INSTRUCTION
Start
SC  0
AR  PC
T0
IR  M[AR], PC  PC + 1
T1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)
(Register or I/O) = 1
(I/O) = 1
I
T3
Execute
input-output
instruction
SC  0
D'7IT3:
D'7I'T3:
D7I'T3:
D7IT3:
D7
= 0 (Memory-reference)
= 0 (register)
(indirect) = 1
T3
Execute
register-reference
instruction
SC  0
T3
AR  M[AR]
= 0 (direct)
I
T3
Nothing
Execute
memory-reference
instruction
SC  0
AR M[AR]
Nothing
Execute a register-reference instr.
Execute an input-output instr.
T4
Instruction Cycle
REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
CLA
CLE
CMA
CME
CIR
CIL
INC
SPA
SNA
SZA
SZE
HLT
r:
rB11:
rB10:
rB9:
rB8:
rB7:
rB6:
rB5:
rB4:
rB3:
rB2:
rB1:
rB0:
SC  0
AC  0
E0
AC  AC’
E  E’
AC  shr AC, AC(15)  E, E  AC(0)
AC  shl AC, AC(0)  E, E  AC(15)
AC  AC + 1
if (AC(15) = 0) then (PC  PC+1)
if (AC(15) = 1) then (PC  PC+1)
if (AC = 0) then (PC  PC+1)
if (E = 0) then (PC  PC+1)
S  0 (S is a start-stop flip-flop)
MR Instructions
MEMORY REFERENCE INSTRUCTIONS
Symbol
AND
ADD
LDA
STA
BUN
BSA
ISZ
Operation
Decoder
D0
D1
D2
D3
D4
D5
D6
Symbolic Description
AC  AC  M[AR]
AC  AC + M[AR], E  Cout
AC  M[AR]
M[AR]  AC
PC  AR
M[AR]  PC, PC  AR + 1
M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
-The effective address of the instruction is in AR and was placed there during timing
signal T2 when I = 0, or during timing signal T3 when I = 1
-Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4:
D0T5:
ADD to AC
D1T4:
D1T5:
DR  M[AR]
AC  AC  DR, SC  0
Read operand
AND with AC
DR  M[AR]
AC  AC + DR, E  Cout, SC  0
Read operand
Add to AC and store carry in E
MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4
20
PC = 21
0
BSA
135
Next instruction
AR = 135
136
Subroutine
1
BUN
Memory
135
Memory, PC after execution
20
0
BSA
135
21
Next instruction
135
21
Subroutine
PC = 136
1
BUN
Memory
135
MR Instructions
MEMORY REFERENCE INSTRUCTIONS
BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ: Increment and Skip-if-Zero
D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
MR Instructions
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Memory-reference instruction
AND
D0 T 4
DR  M[AR]
ADD
LDA
D1 T 4
DR  M[AR]
D0 T 5
D1 T 5
AC  AC  DR
AC  AC + DR
SC  0
E  Cout
SC  0
BUN
BSA
STA
D2 T 4
DR  M[AR]
D2 T 5
AC  DR
SC  0
ISZ
D4 T 4
D5 T 4
D6 T 4
PC  AR
M[AR]  PC
DR  M[AR]
SC  0
AR  AR + 1
D5 T 5
PC  AR
SC  0
D6 T 5
DR  DR + 1
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
D 3T 4
M[AR]  AC
SC  0
I/O and Interrupt
INPUT-OUTPUT AND INTERRUPT
A Terminal with a keyboard and a Printer
• Input-Output Configuration
Input-output
terminal
Printer
Serial
communication
interface
Computer
registers and
flip-flops
Receiver
interface
OUTR
FGO
AC
INPR
OUTR
FGI
FGO
IEN
Input register - 8 bits
Output register - 8 bits
Input flag - 1 bit
Output flag - 1 bit
Interrupt enable - 1 bit
Keyboard
Transmitter
interface
INPR
FGI
Serial Communications Path
Parallel Communications Path
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
I/O and Interrupt
PROGRAM CONTROLLED DATA TRANSFER
-- CPU --
-- I/O Device --
/* Input */
/* Initially FGI = 0 */
loop: If FGI = 0 goto loop
AC  INPR, FGI  0
loop: If FGI = 1 goto loop
/* Output */
/* Initially FGO = 1 */
loop: If FGO = 0 goto loop
OUTR  AC, FGO  0
loop: If FGO = 1 goto loop
INPR  new data, FGI  1
consume OUTR, FGO  1
FGI=0
FGO=1
Start Input
Start Output
FGI  0
yes
FGI=0
AC  Data
yes
FGO=0
no
no
OUTR  AC
AC  INPR
FGO  0
yes
More
Character
no
END
yes
More
Character
no
END
INPUT-OUTPUT INSTRUCTIONS
D7IT3 = p
IR(i) = Bi, i = 6, …, 11
INP
OUT
SKI
SKO
ION
IOF
p:
pB11:
pB10:
pB9:
pB8:
pB7:
pB6:
SC  0
AC(0-7)  INPR, FGI  0
OUTR  AC(0-7), FGO  0
if(FGI = 1) then (PC  PC + 1)
if(FGO = 1) then (PC  PC + 1)
IEN  1
IEN  0
Clear SC
Input char. to AC
Output char. from AC
Skip on input flag
Skip on output flag
Interrupt enable on
Interrupt enable off
I/O and Interrupt
PROGRAM-CONTROLLED INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input
LOOP,
SKI DEV
BUN LOOP
INP DEV
Output
LOOP,
LOP,
LDA
SKO
BUN
OUT
DATA
DEV
LOP
DEV
INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.
- The I/O interface, instead of the CPU, monitors the I/O device.
- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU
- Upon detecting an interrupt, the CPU stops momentarily the task
it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.
* IEN (Interrupt-enable flip-flop)
- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted
FLOWCHART FOR INTERRUPT CYCLE
I/O and Interrupt
R = Interrupt f/f
Instruction cycle
=0
IEN
=1
=1
=1
Interrupt cycle
Store return address
in location 0
M[0]  PC
Fetch and decode
instructions
Execute
instructions
R
=0
Branch to location 1
PC  1
FGI
=0
=1
FGO
IEN  0
R0
=0
R1
-The interrupt cycle is a HW implementation of a branch and save return address
operation.
-At the beginning of the next instruction cycle, the instruction that is read from
memory is in address 1.
-At memory address 1, the programmer must store a branch instruction that sends
the control to an interrupt service routine
- The instruction that returns the control to the original program is "indirect BUN 0"
I/O and Interrupt
REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE
Memory
Before interrupt
0
1
0
BUN
1120
Main
Program
255
PC = 256
After interrupt cycle
0
PC = 1
0
I/O
Program
1
BUN
1120
Main
Program
255
256
1120
1120
256
BUN
I/O
Program
0
1
BUN
0
Register Transfer Statements for Interrupt Cycle
- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1
- The fetch and decode phases of the instruction cycle
must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Data Transfer and Manipulation
Typical data transfer instructions
Name
Load
Store
Move
Exchange
Input
Output
Push
Pop
Mnemonic
LD
ST
MOV
XCH
IN
OUT
PUSH
POP
85
Eight addressing modes for the load
instruction
Mode
Direct address
Indirect address
Relative address
Immediate operand
Index addressing
Register
Register indirect
Autoincrement
Assembly
Convention
LD ADR
LD @ADR
LD $ADR
LD #NBR
LD ADR(X)
LD R1
LD (R1)
LD (R1)+
Register transfer
AC  M[ADR]
AC  M[M[ADR]]
AC  M[PC + ADR]
AC  NBR
AC  M[ADR + XR]
AC  R1
AC  M[R1]
AC  M[R1], R1  R1 + 1
86
Typical arithmetic instructions
Name
Increment
Decrement
Add
Subtract
Multiply
Divide
Add with carry
Subtract with borrow
Negate (2’s complement)
Mnemonic
INC
DEC
ADD
SUB
MUL
DIV
ADDC
SUBB
NEG
87
Typical logical and bit manipulation
instructions
Name
Clear
Complement
AND
OR
Exclusive-OR
Clear carry
Set carry
Complement carry
Enable interrupt
Disable interrupt
Mnemonic
CLR
COM
AND
OR
XOR
CLRC
SETC
COMC
EI
DI
88
Typical shift instructions
Name
Logical shift right
Logical shift left
Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Rotate right through carry
Rotate left through carry
Mnemonic
SHR
SHL
SHRA
SHLA
ROR
ROL
RORC
ROLC
89
Stack Organization
• Stack: A storage device that stores information in such a
manner that the item stored last is the first item retrieved.
• Also called last-in first-out (LIFO) list. Useful for
compound arithmetic operations and nested subroutine
calls.
• Stack pointer (SP): A register that holds the address of the
top item in the stack.
SP always points at the top item in the stack
• Push: Operation to insert an item into the stack.
• Pop: Operation to retrieve an item from the stack.
REGISTER STACK
A stack can be organized as a collection of a finite
number of registers.
• In a 64-word stack, the stack pointer contains 6 bits.
• The one-bit register FULL is set to 1 when the stack
is full;
EMPTY register is 1 when the stack is empty.
• The data register DR holds the data to be written into
or read from the stack.
The following are the micro-operations associated with
the stack
• Initialization
SP 0, EMPTY 1, FULL 0
Push
SP SP + 1
M[SP] DR
If (SP = 0) then (FULL 1)
Note that SP becomes 0 after 63
EMPTY 0
Pop
DR M[SP]
SP SP - 1
If (SP = 0) then (EMPTY 1)
FULL 0
STACK OPERATIONS
REVERSE POLISH NOTATION (postfix)
•
•
Reverse polish notation :is a postfix notation (places operators after operands)
(Example)
Infix notation
A+B
Reverse Polish notation
AB+
also called postfix.
A stack organization is very effective for evaluating arithmetic expressions
A * B + C * D  (AB *)+(CD *)  AB * CD * +
( 3 * 4 ) + ( 5 * 6 )  34 * 56 * +
Evaluation procedure:
n1. Scan the expression from left to right.
2. When an operator is reached, perform the operation with the two operands found on the left
n side of the operator.
3. Replace the two operands and the operator by the result obtained from the operation.
n (Example)
n
infix 3 * 4 + 5 * 6 = 42
postfix 3 4 * 5 6 * +
n
12 5 6 * +
12 30 +
42
• Reverse Polish notation evaluation with a stack.
Stack is the most efficient way for evaluating arithmetic expressions.
stack evaluation:
Get value
If value is data: push data
Else if value is operation: pop, pop
evaluate and push.
(Example) using stacks to do this.
3 * 4 + 5 * 6 = 42
=> 3 4 * 5 6 * +
Instruction Formats
The most common fields in instruction formats are:
1. Mode field: Specifies the way the effective address is determined
2. Operation code: Specifies the operations to be performed.
3. Address field: Designates a memory address or a processor register
Mode
Opcode
Address
•Zero address instruction: Stack is used. Arithmetic operation pops two operands
from the stack and pushes the result.
• One address instructions: AC and memory. Since the accumulator always
provides one operand, only one memory address needs to be specified.
•Two address instructions: Two address registers or two memory locations are
specified, one for the final result.
•Three address instructions: Three address registers or memory locations are
specified, one for the final result.
It is also called general address organization.
Zero address instructions
Instruction: ADD
Push and pop operations need to specify one address involved in data transfer.
Stack-organized computer does not use an address field for the instructions ADD, and MUL
Instruction: POP X
Evaluate X = ( A + B ) * ( C + D )
PUSH, and POP instructions need an address field to specify the operand
PUSH
A
TOS  A
PUSH
B
TOS  B
TOS  ( A  B )
PUSH
C
TOS  C
PUSH
D
ADD
TOS  D
TOS  (C  D)
MUL
TOS  (C  D)  ( A  B )
ADD
POP
X
X  TOS
Advantages:
No memory addresses needed during the operation.
Disadvantages: results in longer program codes.
One address instructions
•
•
•
One address can be a register name or memory address.
SINGLE ACCUMULATOR ORGANIZATION
Since the accumulator always provides one operands, only one memory address
needs to be specified.
Instruction: ADD X
Microoperation: AC AC + M[X]
LOAD
A
ADD
B
STORE T
AC  M [ A]
AC  AC  M [ B]
M [T ]  AC
• All operations are done between the AC register and memory operand.
• Advantages: fewer bits are needed to specify the address.
Disadvantages: results in writing long programs.
Two address instructions
• Assumes that the destination address is the same as that of the first
operand. Can be a memory address or a register name.
• Instruction: ADD R1, R2
Microoperation: R1  R1 + R2
MOV
R1, A
MOV
R2, B
ADD
R1, R2
MOV
X, R1
R1  M [ A]
R 2  M [ B]
R1  R1  R 2
M [ x]  R1
•
most common in commercial computers
•
•
•
Each address fields specify either a processor register or a memory operand
Advantages: results in writing medium size programs
Disadvantages: more bits are needed to specify two addresses.
Three address organization
GENERAL REGISTER ORGANIZATION
• Three address instructions: Memory addresses for the two operands and one
destination need to be specified.
Instruction: ADD R1, R2, R3
Microoperation: R1  R2 + R3
• Advantages:
results in writing short programs
• Disadvantages: more bits are needed to specify three addresses.
ADD
R1, R2, R3
R1  R 2  R3
Reduced Instruction Set Computer (RISC)
Introduction
• The trend into computer hardware complexity was
influenced by various factors:
– Upgrading existing models to provide more customer applications
– Adding instructions that facilitate the translation from high-level
language into machine language programs
– Striving to develop machines that move functions from software
implementation into hardware implementation
• A computer with a large number of instructions is classified
as a complex instruction set computer (CISC).
• A computer use fewer instructions with simple constructs so
they can be executed much faster within the CPU without
having to use memory as often. It is classified as a reduced
instruction set computer (RISC).
99
Introduction(cont.)
• One reason for the trend to provide a complex
instruction set is the desire to simplify the
compilation and improve the overall computer
performance.
• The essential goal of a CISC architecture is to
attempt to provide a single machine insruction for
each statement that is written in a high-level
language.
• Example of CISC architecture are the DEC VAX
computer and the IBM 37 0computer.
100
CISC characteristics
• The major characteristics of CISC architecture
are:
– A large number of instructions– typically from 100 to 250
instructions
– Some instructions that perform specialized tasks and are used
infrequently
– A large variety of addressing modes—typically from 5 to 20
different modes
– Variable-length instruction formats
– Instructions that manipulate operands in memory
101
RISC characteristics
• The major characteristics of a RISC
processor are:
– Relatively few instructions
– Relatively few addressing modes
– Memory access limited to load and store
instructions
– All operations done within the registers of the
CPU
– Fixed-length, easily decoded instruction format
– Single-cycle instruction execution
– Hardwired rather than microprogrammed control
102
RISC characteristics(cont.)
• Other characteristics attributed to RISC architecture are:
– A relatively large number of registers in the processor unit
– Use of overlapped register windows to speed-up procedure call and
return
– Efficient instruction pipeline
– Compiler support for efficient translation of high-level language
programs into machine language programs
• Studies that show improved performance for RISC
architecture do not differentiate between the effects of the
reduced instruction set and the effects of a large register
file.
– A large number of registers in the processing unit are sometimes
associated with RISC processors.
103
Overlapped register windows
• Some computers provide multiple-register banks, and each
procedure is allocated its own bank of registers. This eliminates
the need for saving and restoring register values.
• Some computers use the memory stack to store the parameters
that are needed by the procedure, but this required a memory
access every time the stack is accessed.
• A characteristics of some RISC processors is their use of
overlapped register windows to provide the passing of
parameters and avoid the need for saving and restoring register
values.
• The concept of overlapped register windows is illustrated in Fig.
8-9.
104
Overlapped register
windows(cont.)
• In general, the organization of register windows will have the
following relationships:
number of global registers = G
number of local registers in each window = L
number of registers common to two windows = C
number of windows = W
• The number of registers available for each window is
calculated as followed:
window size = L + 2C + G
• The total number of registers needed in the processor is
register file = (L + C)W + G
• The example of Fig. 8-9:
105
Overlapped register windows
R15
Common to D and A
R10
R73
Local to D
R64
R63
Common to C and D
R58
Proc D
R57
R48
Local to C
R47
Common to B and C
R42
Proc C
R41
Local to B
R32
R31
R9
R0
Global
registers
Common to all
procedures
Common to A and B
R26
Proc B
R25
R16
Local to A
R15
R10
Proc A
Common to A and D
10
6
Berkeley RISC I
• The Berkeley RISC I is a 32-bit integrated circuit CPU.
– It supports 32-bit address and either 8-, 16-, or 32-bit
data.
– It has a 32-bit instruction format and a total of 31
instructions.
– There are three basic addressing modes:
• Register addressing, immediate operand, and relative to PC
addressing for branch instructions.
– It has a register file of 138 registers
• 10 global register and 8 windows of 32registers in each
– The 32 registers in each window have an organization
similar to the one shown in Fig. 8-9.
107
Berkeley RISC I(cont.)
• Fig. 8-10 shows the 32-bit instruction formats used for
register-to-register instructions and memory access
instructions.
• Seven of the bits in the operation code specify an operation,
and the eighth bit indicates whether to update the status bits
after an ALU operation.
• For register-to-register instructions :
– The 5-bit Rd field select one of the 32 rgisters as a destination for the
result of the operation
– The operation is performed with the data specified in fields Rs and
S2.
– Thus the instruction has a three-address format, but the second
source may be either a register or an immediate operand.
108
Berkeley RISC I(cont.)
• For memory access instructions:
– Rs to specify a 32-bit address in a register
– S2 to specify an offset
– Register R0 contains all 0’s, so it can be used in any
field to specify a zero quantity
• The third instruction format combines the last three
fields to form a 19-bit relative address Y and is
used primarily with the jump and call instructions.
– The COND field replaces the Rd field for jump
instructions and is used to specify one of 16 possible
branch conditions.
109
Berkeley RISC I instruction formats
31
24
23
Opcode
8
19
18
14 13
12
Rd
Rs
0
5
5
1
5
Not used
4
0
S2
8
5
(a) Register mode: (S2 specifies a register)
31
24
23
Opcode
8
19
18
14 13
12
Rd
Rs
1
5
5
1
0
S2
13
(b) Register-immediate mode: (S2 specifies an operand )
31
24
Opcode
8
23
19
18
0
COND
Y
5
19
(c) PC relative mode:
110
Instruction set of berkeley RISC I
• The 31 instructions of RISC I are listed in
Table8-12.
• They have been grouped into three categories:
– The data manipulation instructions:
• Perform arithmetic, logic, and shift operations.
• An immediate operand is symbolized by the number sign #.
ADD R22, R21, R23
ADD R22, #150, R23
ADD R0, R21, R22
ADD R0, #150, R22
ADD R22, #1, R22
R23  R22 + R21
R23  R22 + 150
R22  R21 (Move)
R22  150 (Load immediate)
R22  R22 + 1 (Increment)
111
Instruction set of berkeley RISC I
– The data transfer instructions:
• Consist of six load instructions, three store instructions, and
two instructions that transfer the program status word PSW.
• PSW contains the status of the CPU and includes the
program counter, the status bits from the ALU, pointers used
in conjunction with the register windows, and other info. That
determine the state of the CPU.
LDL (R22)#150, R5
LDL (R22)#0, R5
LDL (R0)#500, R5
R5  M[R22] + 150
R5  M[R22]
R5  M[500]
– The program control instructions:
• Operate with the program counter PC to control the program
sequence
• One uses an index plus displacement addressing
• The second uses a relative to PC mode with the 19-bit Y
value as the
112
relative address
Instruction set of berkeley RISC I
Opcode
Operands
Register transfer
Description
Data manipulation instructions
ADD
ADDC
SUB
SUBC
SUBR
SUBCR
AND
OR
XOR
SLL
SRL
SRA
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rs,S2,Rd
Rd  Rs + S2
Rd  Rs + S2 + carry
Rd  Rs - S2
Rd  Rs - S2 - carry
Rd  S2 – Rs
Rd  S2 – Rs – carry
Rd  Rs S2
Rd  Rs V S2
Rd  Rs S2
Rd  Rs shifted by S2
Rd  Rs shifted by S2

Rd  Rs shifted by S2
Integer add
Add with carry
Integer subtract
Subtract with carry
Subtract reverse
Subtract with carry
AND
OR
Exclusive-OR
Shift-left
Shift-right logical
Shift-right arithmetic
113
Instruction set of berkeley RISC I(cont.)
Opcode
Operands
Register transfer
Description
Data transfer instructions
LDL
LDSU
unsigned
LDSS
LDBU
LDBS
LDHI
STL
STS
STB
GETPSW
PUTPSW
(Rs)s2,Rd
(Rs)s2,Rd
Rd  M[Rs + S2]
Rd  M[Rs + S2]
(Rs)s2,Rd
(Rs)s2,Rd
(Rs)s2,Rd
Rd,Y
Rd,(Rs)S2
Rd,(Rs)S2
Rd,(Rs)S2
Rd
Rd
Rd  M[Rs + S2]
Rd  M[Rs + S2]
Rd  M[Rs + S2]
Rd  Y
M[Rs + S2]  Rd
M[Rs + S2]  Rd
M[Rs + S2]  Rd
Rd  PSW
PSW  Rd
Load long
Load short
Load short signed
Load byte unsigned
Load byte signed
Load immediate high
Store long
Store short
Store byte
Load status word
Set status word
114
Instruction set of berkeley RISC I(cont.)
Opcode
Operands
Register transfer
Description
Program control instructions
JMP
COND,S2(Rs)
PC  Rs + S2
JMPR
COND,Y
PC  PC + Y
CALL
Rd,S2(Rs)
CALLR
Rd,Y
RET
Rd,S2
CALLINT
Rd
RETINT
Rd,S2
GTLPC
Rd
Rd  PC
PC  Rs + S2
CWP  CWP –1
Rd  PC
PC  PC + Y
CWP  CWP – 1
PC  Rd + S2
CWP  CWP + 1
Rd  PC
CWP  CWP –1
PC  Rd + S2
CWP  CWP + 1
Rd  PC
Conditional jump
Jump relative
Call subroutine
and
change window
Call relative
and
change window
Return and
change window
Disable interrupts
Enable interrupt
Get last PC
11
5