UNIT 5 Procedures, Tasks, and Functions
6.1 Highlights of Procedures, Tasks, and Functions
Facts
Procedures, Tasks, and Functions are HDL tools to optimize the style of
writing the HDL code. They are implemented to refer to a segment
or a construct of code.
Procedures and Tasks can have more than one input and more than
one output. Functions have single output but can have more than one input.
Procedures and Functions in VHDL can be called only from within process.
Tasks and Functions in Verilog can be called only from within
always or initial.
HDL Programming Fundamentals
6.2 Procedures (VHDL) and Tasks (Verilog)
procedure exmple (signal a : in std_logic ; signal y: out std_logic) is
variable x: std_logic;
begin
x:= a;
exmple is the name
case x is
(identifier) of
.......
the procedure
end case;
y <= x;
end exmple;
Calling the procedure is a sequential statement
process (d,clk)
begin
......
exmple (d,z);
.........
End process
HDL Programming Fundamentals
task addr;
output cc, dd;
input aa, bb;
begin
cc = aa ^ bb;
.............
end
endtask
addr is the name
(identifier) of
the task
............
always @ (a,b)
begin
addr( c,d,a,b);
end
HDL Programming Fundamentals
Example 6.1 HDL Behavioral Description of Full Adder using Procedure
and Task
x
sum
y
cin
Half adder
Half adder
carry
HDL Programming Fundamentals
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_add is
port (x,y, cin: in std_logic; sum, cout: out std_logic);
end full_add;
architecture two_halfs of full_add is
-- The full adder is built from two half adders
procedure Haddr(sh, ch: out std_logic; ah, bh : in std_logic) is
--This procedure describes a half adder
begin
sh := ah xor bh;
ch := ah and bh;
end Haddr;
begin
addfull: process (x,y,cin)
variable sum1, c1, c2, tem1, tem2: std_logic;
begin
Haddr (sum1, c1, y, cin);
Haddr( tem1, c2, sum1,x);
--The above two statements are calls to the procedure Haddr
tem2:= c1 or c2;
sum <= tem1;
cout <= tem2;
end process;
end two_halfs;
HDL Programming Fundamentals
Verilog
module Full_add(x,y,cin,sum, cout);
//The full adder is built from two half adders
input x,y, cin;
output sum, cout;
reg sum,sum1,c1,c2, cout;
always @ (x,y, cin)
begin
Haddr( sum1,c1,y,cin );
Haddr( sum, c2, sum1,x);
//The above two statements are calls to the task Haddr.
cout = c1 | c2;
end
task Haddr;
//This task describes half adder
output sh, ch;
input ah, bh;
begin
sh = ah ^ bh;
ch = ah & bh;
end
endtask
endmodule
HDL Programming Fundamentals
Example 6.2 HDL Description of N-bit Ripple-Carry Adder using Procedure
and Task
Listing 6.2
HDL Programming Fundamentals
Example 6.3 Unsigned Binary Vector to Integer Conversion
using Procedure and Task
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
entity Bin_Int is
generic (N : natural :=3);
port (X_bin: unsigned (N downto 0);
Y_int: out natural; Z: out std_logic);
--Y is always positive
end Bin_Int;
architecture convert of Bin_Int is
procedure bti (bin : in unsigned ; int: out natural;
signal Z: out std_logic) is
-- the procedure bti is to change binary to integer
--We chose flag Z to be a signal rather than a variable
-- Since the binary vector is always positive we use natural
variable result:natural;
begin
result := 0;
for i in bin'Range loop
--bin’Range represents the range of the unsigned vector bin
--Range is a predefined attribute
HDL Programming Fundamentals
Verilog
module Bin_Int(X_bin, Y_int, Z);
parameter N =3;
input [N:0] X_bin;
output integer Y_int;
output Z;
reg Z;
always @ (X_bin)
begin
bti(Y_int,Z, N, X_bin);
end
task
bti;
parameter P = N;
output integer int;
output Z;
input N;
input [P:0] bin;
integer i, result;
begin
int =0;
//change binary to integer
for (i=0; i<=P; i=i+1)
begin
if (bin[i] == 1)
int = int + 2**i;
end
if (int == 0)
Z = 1'b1;
else
Z = 1'b0;
end
endtask
endmodule
HDL Programming Fundamentals
Example 6.4 Fraction Binary to Real Conversion using Procedure and Task
Listing 6.4
HDL Programming Fundamentals
Example 6.5 Unsigned Integer to Binary Conversion using Procedure and Task
Listing 6.5
HDL Programming Fundamentals
Example 6.6 Signed Binary to Integer Conversion using Procedure and Task
Listing 6.6
HDL Programming Fundamentals
Example 6.7 Integer to Signed Binary Conversion using procedure
Listing 6.7
HDL Programming Fundamentals
Example 6.8 Signed Vector Multiplication Using Procedure and Task
Listing 6.8
HDL Programming Fundamentals
Example Enzyme-Substrate Activity Using procedure and task
Listing 6.9
HDL Programming Fundamentals
6.3 Functions
VHDL
architecture Behavioral of Func_exm is
function exp (a, b: in std_logic) return std_logic
variable d: std_logic;
begin
d := a xor b;
return d;
exp is the name (identifier)
end function exp;
of the function
Verilog
function exp ;
input a,b;
begin
exp = a ^ b;
end
endfunction
HDL Programming Fundamentals
is
Example 6.10 Function to Find the Greater of two signed numbers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity greater_2 is
port (x,y : in signed (3 downto 0) ; z: out signed (3 downto 0));
end greater_2;
architecture greater_2 of greater_2 is
function grt(a,b : signed (3 downto 0)) return signed is
--The above statement declares a function by the name of grt.
-- The inputs are 4-bit signed numbers
variable temp : signed (3 downto 0);
begin
if (a >= b) then
temp := a;
else
temp := b;
end if;
VHDL
return temp;
end grt;
begin
process (x,y)
begin
z <= grt (x,y); --This is a function call.
end process;
end greater_2;
HDL Programming Fundamentals
module greater_2(x,y, z);
input signed [3:0] x;
Verilog
input signed [3:0] y;
output signed [3:0] z;
reg signed [3:0] z;
always @ (x,y)
begin
z = grt (x,y);//This is a function call.
end
function [3:0] grt;
/*The above statement declares a function by the name grt;
grt is also the output of the function*/
input signed [3:0] a, b;
/*The above statement declares two input to the function;
both are 4-bit signed numbers.*/
begin
if (a >= b)
grt = a;
else
grt = b;
end
endfunction
endmodule
HDL Programming Fundamentals
3
Example Function to Find the floating sum y =
 (  1)
i0
Listing 6.13
HDL Programming Fundamentals
i
(x)
i
,
0<x<1
6.4 Summary
VHDL Commands or Components
procedure
function
HDL Programming Fundamentals
Verilog Counterpart
task
function