EE 370A – Monsoon 2019
Indian Institute of Technology Kanpur
Department of Electrical Engineering
Practice Problems – 4
Due: Friday 30th August, 2019
1.
Consider a CMOS inverter in which p & n devices are not matched. The parameters are:
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W
VDD = 5 V, ( )p = ( )n, Kn = 81 A V-2, Kp = 27 A V-2, Vtn = |Vtp| = 0.75 V
L
L
Derive the analytical expression for the inverter threshold voltage. Using that expression, find the
threshold voltage of the inverter.
2.
A CMOS inverter in a VLSI circuit is operating from a 5 V supply. It is given that
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( )n = (10 m/ 5 m); ( )p = (20 m/ 5 m); Vtn = |Vtp| = 1 V; and n Cox = 2 p Cox = 20 A V-2
L
L
The total effective load capacitance is 0.1 pF. Find tpHL, tpLH, tp, by the following four methods:
(i) Estimate the dc resistances for initial value of output and when the output is mid-point of its value
between the initial and final values. Use these values to find average resistance of the transistor and
hence the various propagation delay time.
(ii) Assume the transistor is a constant current source when in the saturation region. In the linear
region, assume the average current to/from the capacitor is the arithmetic mean of the currents in the
transistors when at the edge of the saturation region and when output is at the mid-value between the
initial and final value because of the switching. Use these current values to estimate the time taken to
discharge the load capacitance to the voltages of interest.
(iii) Find the average of the current when the output voltage is at the initial value and final value of
interest. Use this current to compute the time taken to charge / discharge the load capacitor. How
different is this value from that found in (i)?
(iv) Simulate the circuit using SPICE and determine the various propagation delays.
Tabulate the results of the four approaches and share any insight you get from comparing the results.
3. For the CMOS inverter described in question 2, determine the rise and fall time at the output of the
inverter (10% to 90% of the transitions) by analytical methods using appropriate approximations and
by simulation using SPICE.
4. For the CMOS inverter described in question 2, determine the maximum short circuit current if the
input voltage is changed slowly w.r.t. the output. Verify this value using SPICE simulations. What
should be the minimum rate at which the input has to switch in order to keep the short circuit power
dissipation less than 10% of the switching power dissipation? Assume load capacitance to be 0.1 pF as
in question 2.