International Journal of Electronics
ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20
Area efficient layout design of CMOS circuit for
high-density ICs
Vimal Kumar Mishra & R. K. Chauhan
To cite this article: Vimal Kumar Mishra & R. K. Chauhan (2018) Area efficient layout design
of CMOS circuit for high-density ICs, International Journal of Electronics, 105:1, 73-87, DOI:
10.1080/00207217.2017.1340978
To link to this article: http://dx.doi.org/10.1080/00207217.2017.1340978
Accepted author version posted online: 08
Jun 2017.
Published online: 21 Jun 2017.
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Date: 25 October 2017, At: 04:02
INTERNATIONAL JOURNAL OF ELECTRONICS, 2018
VOL. 105, NO. 1, 73–87
https://doi.org/10.1080/00207217.2017.1340978
Area efficient layout design of CMOS circuit for high-density ICs
Vimal Kumar Mishra and R. K. Chauhan
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Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology,
Gorakhpur, India
ABSTRACT
ARTICLE HISTORY
Efficient layouts have been an active area of research to accommodate
the greater number of devices fabricated on a given chip area. In this
work a new layout of CMOS circuit is proposed, with an aim to improve
its electrical performance and reduce the chip area consumed. The study
shows that the design of CMOS circuit and SRAM cells comprising
tapered body reduced source fully depleted silicon on insulator (TBRS
FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI nand p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff
ratio when compared with FD-SOI MOSFET and FinFET technology. Other
parameters like power dissipation, delay time and signal-to-noise margin
of CMOS inverter circuits show improvement when compared with
available inverter designs. The above device design is used in 6-T
SRAM cell so as to see the effect of proposed layout on high density
integrated circuits (ICs). The SNM obtained from the proposed SRAM cell
is 565 mV which is much better than any other SRAM cell designed at
50 nm gate length MOS device. The Sentaurus TCAD device simulator is
used to design the proposed MOS structure.
Received 16 September 2016
Accepted 7 June 2017
KEYWORDS
Tapered Body Reduced
Source (TBRS); area
consumed; switching ratio
(Ion/Ioff); FD-SOI MOSFET;
CMOS circuit; 6-T SRAM cell
1. Introduction
The silicon area consumed a CMOS circuit which comprises the n-MOS and p-MOS structure, and is
main concern for most researchers. Since last two decades, the economical layout of integrated
circuits (ICs) is an important issue and has been an active area of research. The efficient layout of
ICs has been proposed by several researchers so as to accommodate a greater number of devices
on it (Lu, 2014; Saremi, Afzali-Kusha, & Mohammadi, 2012; Sun, Hsiung, & Yi, 2004; Yeh, Lin, Chou,
Wu, & Yuan, 2015).
Initially, the structure of CMOS involves separate n-MOS and p-MOS transistor layout with
interconnections in U-shaped in an inverter circuit. Although this U-shaped circuit results in a
high density of CMOS devices, their interconnections cause problems in designing certain circuits.
Sun et al. (2004) proposed a Z-shaped interconnection-based CMOS circuit. In this, the two MOS
transistors were interconnected with its gate coupled to each other in a Z-shape. This circuit
configuration has some drawback as it uses large chip area. Lu (2014) proposes a computerimplemented method for designing the layout of a multi-finger CMOS circuit for getting improved
drain current. The drawback of multi-fingering structure was also the same; it also requires larger
chip area and increased connection wire resistances that complex the fabrication process.
The major challenges associated with current CMOS technology are: the supply voltage scaling,
Vth roll off, off-state leakage current and power consumption. To overcome these challenges,
CONTACT R. K. Chauhan
rkcece@mmmut.ac.in
Department of Electronics and Communication Engineering, Madan
Mohan Malaviya University of Technology, Gorakhpur, India
© 2017 Informa UK Limited, trading as Taylor & Francis Group
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74
V. K. MISHRA AND R. K. CHAUHAN
researchers have proposed different types of MOSFET-based (such as SOI MOSFETs, FinFETs, SOI
FinFETs, V-TFT, Tunnel FETS, etc.) CMOS circuits.
Yeh et al. (2015) had discussed the impact of junction doping in the design of FD SOI MOSFET
with thin insulator (box) layer. Saremi et al. (2012) analysed the ground plane SOI FinFETs used for
low leakage power circuits. Le et al. (2011) proposes a vertical nanowire thin-film transistor (V-TFT)
CMOS circuit, in which the CMOS performance has been analysed by the use of gate-all-around
(polycrystalline silicon vertical nanowire) TFTs. These devices have low Ion/Ioff ratio in n-MOS and
p-MOS structures, and high off-state current due to which power consumption was a major
concern for these circuits. In another work, Pal, Kaushik, and Member (2014) discussed the dualspacer trigate FinFET inverter circuit in which the supply voltage was scaled till 0.6 V, but this circuit
has fabrication complexity and area consumption. Kaushal et al. (2014) have proposed a CMOS
logic circuit with extension length as a tuning parameter that comprises of nano wire FET with nand p-FET at 10 nm gate length. The transient analysis of this inverter circuit shows larger delay [7].
Low power consumption in an inverter circuit is also an area of interest for researchers. Sahu
and Singh (2014) had discussed the doping-less silicon on insulator structure using double gate for
low power digital applications. The drawback of this circuit is that it uses the double gate and
consumes more area [8].
Another important parameter to characterise any device used in CMOS circuit is its threshold
voltage and sub-threshold slope. Khatami and Banerjee (2009) proposed a MOS structure that uses
tunnel field effect transistor (TFET)-based CMOS inverter circuit which shows low threshold voltage
contrast with steep threshold slope and better Ion to Ioff ratio. Due to use of silicon-germanium
material in the channel, the structure has fabrication complexity [9].
FD-SOI is a planar process technology that follows Moore’s law in nanometre dimensions. The
FD-SOI MOS structure consists of a top layer is front gate oxide, bottom layer is thin silicon film and
ultra-thin layer of insulator, called the buried oxide (BOX) below the silicon film. Recently, some of
the works depicting the modification in the source region of MOSFET to enhance its electrical
performance have been studied (Chauhan & Mishra, 2017b; Chen et al., 2011). Mishra and Chauhan
(2017a) proposed a tapered body reduced source (TBRS) structure in the design of FD-SOI MOSFET.
This structure has given better solution towards area-efficient design in accord with good electrostatic control as compared to other FD-SOI MOS structures.
In this paper, a layout of compact CMOS inverter circuit is proposed which comprises TBRS FDSOI n- and p-MOSFET. This work exploits the advantages of FD-SOI technology and involves a novel
concept for a designer to form a CMOS structure that reduces the consumed silicon area required
for any MOSFET-based inverter circuit. The electrical performance of this CMOS inverter and 6-T
SRAM cell is also studied using Sentaurus device simulator and compared with the available
reported results.
2. CMOS device structure and specification
As an alternative solution towards achieving less area, a novel MOS device is proposed that has
tapered body with reduced source of n- and p-type MOSFET, overlapped over each other with
tapered small insulated gap between them. In this work, structure-tapered body-reduced source
FD-SOI n- and p-MOSFET are designed first and thereafter used to form compact CMOS circuit.
Some theoretical explanations to support the CMOS circuit behaviour are also presented.
Figure 1(a) shows the conventional method of making FD-SOI CMOS circuit. Figure 1(b) shows
the structure of standard FD-SOI MOS device with tapering section embedded in it. This tapered
section is SiO2 layer separating another device formed beneath it. The area saved because of
tapering, can be utilised for the formation of another MOSFET. If n-MOSFET is taken at the top,
then lower side should be fabricated as p-MOSFET, so as to form compact CMOS structure.
Figure 1(c) shows the TBRS FD-SOI MOSFET-based CMOS structure having silicon thickness at
source, taken as 3 nm and at the drain, it is 10 nm maximum. The channel length is 50 nm and
INTERNATIONAL JOURNAL OF ELECTRONICS
Gate
Gate
Source
P-substrate
75
Drain
STI
Source
Source
N-substrate
Drain
Drain
SiO2 (Insulator)
SiO2
P-substrate
Substrate
(a)
Gate
Source
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Drain
Saved area in source uses for
drain in P MOSFET
SiO2
(b)
Gate
N-Source
P-Substrate
N-Drain
P-Drain
SiO2
N-Substrate
P-Source
Gate
(c)
(d)
Figure 1. Device structure view: (a) traditional method of FD – SOI CMOS inverter circuit structure; (b) TBRS FD-SOI n- and
p-type SOI MOSFET structure; (c) overlapping structure of TBRS FD-SOI n- and p-type SOI MOSFET-based inverter circuit; (d) 3-D
device design of proposed TBRS FD-SOI MOSFET-based inverter circuit.
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V. K. MISHRA AND R. K. CHAUHAN
Table 1. Comparison of different device parameters of proposed structures and FD-SOI n-MOSFET (Yeh et al., 2015).
Parameters
n-MOSFET
(proposed)
p-MOSFET
(proposed)
FDSOI n-MOSFET
(Yeh et al., 2015)
50 nm
1 nm
4.8
5 nm
1e16
1e20
3 nm
10 nm
50 nm
1 nm
4.8
5 nm
1e16
1e20
3 nm
10 nm
50 nm
1.3 nm
4.7
BOX thickness = 20 nm
–
–
Constant Source = 10 nm
Constant Drain = 10 nm
Gate length (nm)
Gate oxide thickness (nm)
Gate workfunction (eV)
Tapered insulator thickness
Substrate doping concenteration (cm−3)
Drain/source doping concentration (cm−3)
Thickness of reduced source region (nm)
Thickness of tapered drain region (nm)
Table 2. Comaprison of area consumed in proposed inverter circuit and the FD-SOI MOSFET-based CMOS inverter circuit (Yeh
et al., 2015).
Plane
FD-SOI MOSFET-based inverter circuit (Yeh et al.,
2015)
TBRS FD-SOI MOSFET-based inverter circuit
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x-plane
100 nm for NMOS + 5 nm for shallow trench
100 nm for NMOS and PMOS (up and down); total length
isolation + 100 nm for PMOS; total length in
in x-plane = 100 nm
x-plane = 205 nm
y-plane
10 nm Si + 5 nm SiO2 + 10 nm substrate thickness; 3 nm for source and 10 nm for drain in NMOS + 5 nm
total length in y-plane = 25 nm
SiO2 + 3 nm for source and area saved underneath the
source is used for drain in PMOS; total length in
y-plane = 13 nm
Total area covered along x and y
Total area Total area covered along x and y
direction = 100 × 13 = 1300 nm−2
direction = 205 × 25 = 5125 nm−2
width of inverter is taking 100 nm. Both diffusion Length (LD) and front gate oxide thickness of the
MOSFET has been taken as 1 nm.
The different parameters are considered for the design of FD-SOI n-MOSFET (Yeh et al., 2015)
and proposed device structures are discussed in the Table 1.
Further, the CMOS inverter circuits are designed using proposed n- and p-structure and FD-SOI
n- and p-MOSFET and its total area consumption are compared in Table 2. On comparison, it can be
articulated that area consumed by the proposed CMOS structure using TBRS FD-SOI n- and
p-MOSFET are approximately four times less area than the area consumed by the CMOS inverter
circuit which comprises FD-SOI MOS structures.
3. CMOS device concept and theory
The SOI MOSFET design is different from bulk conventional MOSFETs; however, this type of device
design exhibits better electrical performance. SOI MOSFETs have an insultor layer present at the
top of the base silicon substrate and afterward a very thin silicon layer forms the channel, which
results in low off-state leakage current. Due to low leakage current, Ioff current reduces. Compared
to bulk conventional MOSFET, the SOI MOSFET has high drive current and negligible threshold
voltage roll off even with minimal threshold voltage of operation. Due to suppression of channel
length modulation effects in the design of SOI MOSFET, the electrical performance of the SOI-based
devices are enhanced in saturation region. The structure of SOI MOSFET-based inverter has been
studied for the following modifications:
(1) Tapering of body and reducing of source of n- and p-type MOSFET
(2) Thickness of Insulator (SiO2) separating the n- and p-type MOSFET
(3) Doping profile in the substrate of the n- and p-type MOSFET
INTERNATIONAL JOURNAL OF ELECTRONICS
77
3.1. Tapering of body and reducing of source of n- and p-type MOSFET
In the proposed TBRS structure, source area has been efficiently optimised compared to other
structures reported in literature and body region area beneath the source has been tapered along
with the other substrate and drain regions with the angle of 45° on the silicon wafer plane (111).
The simulation results show that the thickness of source region of the proposed design can be
optimised till the width of the depletion layer of the channel. Equation (1) helps to calculate the
depletion width of the channel.
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 2 si:j2;F j
Qdm ¼
(1)
qNA
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ni
and ;Fn ¼ VT ln ND
where ;Fp ¼ VT ln NA
ni :
The calculation shows that the minimum depletion width of the channel should be 2 nm for the
above configuration; hence, the source could be optimised to 2 nm depth, which matches with the
simulated results also.
3.2. Insulator (SiO2) separated the n- and p-type MOSFET
In this structure, TBRS FD-SOI n-MOSFET is placed on the TBRS FD-SOI p-MOSFET with tapered
small insulated gap of 5 nm in between them. The performance of the structure degrades when
both TBRS FD-SOI n- and p-types MOSFET are connected without insulator in between them. This is
because of the fact that both the substrate of n- and p-MOSFET connect to each other forming a
diode. Because of which the leakage current increases and the Vout of the proposed CMOS
decreases.
It was also noticed that when the thickness of insulator region reduces to 3 nm or less, the
tunnelling of an electron occurs from the p-type substrate to the n-type substrate which reduces
the performance of the proposed CMOS circuit.
3.3. Doping profile
The doping in the substrate region of TBRS FD-SOI n-type MOSFET is kept at 1e16. The corresponding threshold voltage for the structure is 0.4V, and Ioff and Ion current is 80 fA and 3 mA,
respectively. Hence, Ion/Ioff ratio is 1010, which is better than any other SOI MOSFET at 50 nm
gate length. When doping is increased from 1e16 to 1e18, the threshold voltage increases from 0.4
to 0.5 V and Ioff decreases from 80 fA to 5 fA.Due to lower threshold voltage and lower off-state
current of the proposed device , it has the potential to meet low standby power and low operating
power requirements. In our proposed structure, the profile has been taken as 1e16 in the substrate
region of the n-type MOSFET.
4. CMOS circuit simulation
Extensive device design simulations were made by using Sentaurus Technology Computer Aided
Design (TCAD) device simulator (Sentaurus Device User Guide, Mountain View, (2010)) excelled
with mathematical calculations. The drift-diffusion computation model is utilised by the various
effects such as band-to-band tunnelling, Shockley–Hall–Read, Thomas mobility model mobility and
Auger. Trap-assisted, and surface recombination are also been included by TCAD device simulator.
When the device is simulated, the drive current computed from proposed TBRS MOS structure is
close to the recent testified results (Anvarifard and Orouji 2014; Chen et al., 2011; Khatami &
Banerjee, 2009; Pal et al., 2014; Saremi et al., 2012; Yeh et al., 2015).
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V. K. MISHRA AND R. K. CHAUHAN
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5. Methodology of circuit implementation
In this work, CMOS inverter circuit is implemented using TBRS FD-SOI n- and p-MOS structures. The
schematic of the designed circuit is shown in Figure 2(a) and the design layout is presented in
Figure 2(b). Section (a) represents the top view of p-MOS and section (b) for n-MOS, which will be
below the section (a) in the layout diagram. The reduced source region of the p-MOS structure is
connected to Vdd, and the tapered drain region of n- and p-type TBRS SOI MOSFET is connected to
Vout. The reduced source region of the n-MOS structure is connected to the ground terminal. In this
way, both the n- and p-type TBRS SOI MOSFET device is configured in the form of CMOS circuit.
On comparing the methodology used for circuit simulation of conventional CMOS circuit with
that of proposed CMOS circuit using Sentaurus 2d device simulator, it was found that the conventional CMOS took more time than the proposed one. Figure 2(c) shows the mixed mode simulation
methodology in the form of the flow chart of TBRS structure for SOI n- and p-MOSFET to form
CMOS inverter circuit. In mixed mode simulation, the operation is split into four elements: (1) the nand p-type MOS device descriptions defines in the first part with information about doping
concentration, meshes with inputs of mobility, device geometry, recombination, area, etc.; (2)
after this, the input and output characteristics of devices are simulated and studied; (3) the third
step in the operation involves coupling and net listing of the n-MOS and p-MOS device involved in
the circuit which describe the parameters of the circuit component and its electrical models; (4) the
last step in the implementation involves the application of biasing voltage and its DC and transient
analysis. The simulation runs on the basis of some initial guess for the coupled device and
afterwards for nodal equation of the circuit. Figure 2(d) shows the flow chart of proposed CMOS
inverter for DC and transient analysis. In this flow chart, the input device is coupled CMOS inverter
rather than individual n-MOS and p-MOS devices. The equations are solved directly using Poisson
equation and electron continuity equations considering necessary boundary conditions and inputs.
6. Results and discussion
The input–output characteristics, electric field and potential variation within proposed MOSFET are
simulated using Sentaurus device simulator.
Figure 3(a,b) shows the effect of electric field and electron mobility profile from source to drain
in the x direction of proposed TBRS MOS structure and FD-SOI n-MOSFET at Vgs = 0, 0.3 and 1 V. It
can be inferred from these figures that electric field is quite high in the proposed structure than the
previous FD-SOI MOSFETs at Vgs = 0 V. Figure 3(b) shows that the proposed TBRS structure has
higher mobility of charge carriers in the channel when compared with previous FD-SOI MOSFET at
Vgs = 0 V. Due to this, the off-state current is quite less in the proposed structure. When the gate
voltage is greater than the threshold voltage (Vgs = 0.3 V), the electric field increases near the drain
region which helps to flow constant current from source to drain. Figure 3(c) shows the potential
contour of proposed inverter. The potential is high at the drain side of the n- and p-MOSFET and
minimum potential are seen at the insulator region which is separating the n- and p-MOSFET.
The output characteristics of the FD-SOI MOSFET and proposed structure are shown in Figure 4(a).
One can see from figure that the on-current is more in the proposed structure when it has been
compared with the FD-SOI MOSFET (Yeh et al., 2015). Figure 4(b) presents the impact of various gate
voltages on the output characteristics of TBRS FD-SOI n-MOSFET. Due to the use of 5 nm of tapered
insulator area below the silicon region, the channel length modulation effect is reduced in the
proposed structure which results in low off-state leakage current. The saturated currents of n- and
p-MOS devices are useful in the performance evaluation of inverter DC characteristics for getting
sharp slope in the voltage transfer characteristics (VTC) curve of it. The large driving current helps in
improving transient analysis of inverter circuits.
Figure 5 shows the comparisons of input characteristics of proposed n-MOSFET with FDSOI
MOSFET (Yeh et al., 2015) and SOI FinFET structure (Saremi et al., 2012). The off-state leakage
INTERNATIONAL JOURNAL OF ELECTRONICS
79
Vdd
TBRS p-MOSFET
Vin
TBRS n-MOSFET
gnd
(a)
Section A
Section B
N-well
P-well
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Source
Drain
Drain
Source
(b)
Start
Start
Area, Mobility,
Doping Density
Area, Mobility,
Doping Density
NMOS
PMOS
Proposed Inverter
Plot current and Voltage
Plot current and Voltage
Solve proposed device and circuit
equation using poisson equation
Net listing the PMOS and NMOS
Voltage and
time meet
final value
Solve Coupled device and circuit
equation using poisson equation
Device and Circuit output characteristics
Voltage and
time meet
final value
End
(d)
Device and Circuit output characteristics
End
(c)
Figure 2. Circuit diagram and flow chart of proposed CMOS circuit. (a) CMOS inverter circuit using TBRS SOI n- and p-MOSFET.
The cross using the drain terminal shows the tapering in drain region; (b) layout of proposed CMOS circuit; (c) flow chart of
inverter circuit simulation of traditional simulation in Sentaurus 2d Device simulator; (d) flow chart of proposed inverter circuit
in Sentaurus 2d device simulator.
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80
V. K. MISHRA AND R. K. CHAUHAN
Figure 3. Electric field and potential distribution. (a) The comparison of electric field of proposed TBRS FD-SOI MOSFET with
that of available FD-SOI MOSFET structure (Yeh et al., 2015) at Vgs = 0, 0.3 and 1 V; (b) the comparison of electron mobility of
proposed structure with that of available FD-SOI MOSFET structure (Yeh et al., 2015) at Vgs = 0 V and 1 V; (c) potential
distribution of the proposed inverter in which the potential is higher at the drain side of the n- and p-MOSFET.
Figure 4. Output characteristics curve. (a) The comparison of output characteristics curve of proposed structure with that of
available FD-SOI MOSFET structure (Yeh et al., 2015); (b) TBRS FD-SOI n-MOSFET for gate potential varying from 0.2 V to 1.2 V.
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INTERNATIONAL JOURNAL OF ELECTRONICS
81
Figure 5. The comparison of input characteristics curve of proposed structure with that of available FD-SOI MOSFET structure
(Yeh et al., 2015) and SOI FinFET structure (Saremi et al., 2012), which shows that the Ion to Ioff ratio is higher in the proposed
structure.
current evaluated from the proposed structure was found as 80 fA and drive current as 3 mA. The
switching ratio is then 1010. The minimum subthreshold slope of 55 mV/decade has been obtained
at room temperature. In addition, the proposed structure provides better drive current at 50 nm
gate length as compared to conventional FDSOI n-MOSFET. The threshold voltage of proposed
n-MOSFET structure is 0.3 V.
6.1. TBRS FD-SOI MOSFET-based CMOS circuit performance
6.1.1. DC analysis
The proposed CMOS circuit structure shows improvement in power dissipation, delay time and
signal-to-noise margin also. Figure 6(a) shows the VTC curve of proposed CMOS circuit. The
operation of CMOS inverter circuit is divided into three regions: (1) first one is linear region,
below the input voltage VTo,n, in which p-MOS is on state and n-MOS transistor is cut-off state; (2)
second one is saturation region, when the input voltage surpasses the (Vdd + VTo,p) in which p-MOS
was turned off and n-MOS was turned on; (3) third one is the region between the VTo,n and Vdd+VTo,p;
both the transistors are in saturation regions. The proposed CMOS circuit does not depict any
considerable current from the supply voltage when input voltage is either larger than Vdd+VTo,p or
smaller than VTo,n, apart from low sub-threshold and leakage current. It can be shown in Figure 6(b)
that the utmost current is pinched from the supply voltage through transition region when
Vin = Vm. At this point, both the transistors are operating in saturation mode.
6.1.2. Supply voltage scaling of proposed inverter
The supply voltage Vdd is under consideration for overall power dissipation of any circuit. In present
scenario of industry, the reduction of the power dissipation in large ICs and scaling of the power
supply voltages are most important for the design of low-power digital circuits.
The proposed CMOS circuit is explained correctly at a less supply voltage, which is resulted as
the addition of n- and p-MOSFET threshold voltage.
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82
V. K. MISHRA AND R. K. CHAUHAN
Figure 6. VTC curve and power supply current of proposed inverter circuit. (a) VTC curve of proposed inverter circuit shows
threshold voltage of inverter as 0.7 V which is comparable to that of ideal inverter circuits; (b) the input voltage as a function of
power supply current.
Figure 7. VTC curve of a proposed CMOS inverter circuit at different power supply voltage levels. The supply voltage is scaled
till the summation of the threshold voltage of n-MOS and the p-MOS.
min
Vdd
¼ VT0n þ VT0p (2)
From Figure 7, it is clear that the proposed CMOS circuit performs satisfactorily as an inverter
when input supply voltage is fixed either at 0.2 V or to a larger value to 3 V.
The significant parameters of CMOS inverter circuit that characterise the DC behaviour of the
proposed CMOS inverter circuits is threshold voltage (Vm). Thus, the aim of the design of any CMOS
inverter circuit is to fix the threshold voltage at the desired voltage level.
6.1.3. Transient analysis of proposed CMOS circuit
The transient conduction mechanism of proposed CMOS inverter circuit is presented in Figure 8.
The propagation delay is important concern for the design of any CMOS inverter circuit. The
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INTERNATIONAL JOURNAL OF ELECTRONICS
83
Figure 8. Transient characteristics of proposed inverter circuit which shows negligible delay in the circuit.
propagation delay terms are divided into two terms; first one is Γphl that signify the input to output
signal delay during the high to low and low to high transitions of the output, and second one is
and, Γplh i.e. output to input signal delay during high to low transition. Γphl and Γplh are the similar
associated terms where Γphl defines the delay in transition time of raised voltage (V50%) and fall
voltage (V50%) and Γplh defines delay in transition time of fall in input voltage (V50%) and raised
output voltage (V50%). Average propagation Γp delay of CMOS inverter circuit is defined as the
average time required to propagate signal from the input to the output.
Cload
2Vtn
4ðVdd VtnÞ
Γphl ¼
þ ln
1
(3)
KnðVdd VtnÞ ðVdd VtnÞ
Vdd
Γplh ¼
Cload 2ðVdd jVtpj VoL
2jVtpj ðVdd V50%Þ
þ ln
KpjVtpj
jVtpj
Vdd V50%
Γp ¼
ðΓphl þ ΓplhÞ
2
(4)
(5)
Both p-MOS and n-MOS devices turn on and off when input signal switches from low to high
voltage. Likewise, p-MOS device turns on and n-MOS device is turns off when input signals switch
to high to low voltage. The transient analysis of proposed TBRS FD-SOI MOS-based CMOS inverter
circuit is shown in Figure 7. The obtained Γphl is 5 fs and Γplh is 7 fs, which shows that proposed
circuit has negligible delay and it has also been compared and contrasted by using the analytical
calculations. The analytical calculation almost tracks the simulation results. The analytical results in
the values of Γphl and Γplh are 4 fs and 5.5 fs, respectively.
6.1.4. Noise immunity and noise margins (NMs) of proposed inverter
The noise tolerance for digital circuits is also called as NM. The circuit having better NM has good
noise immunity. NMs are defined in two levels: first one is the NM for low-signal level ðNML Þ and
second one is the NM for high-signal levels (NMH ). Its calculation can be done from equation:
84
V. K. MISHRA AND R. K. CHAUHAN
NML ¼ VIL VOL
(6)
NMH ¼ VOH VIH
(7)
where VOL and VOH are minimum and maximum output voltages, respectively, at logic level ‘0’
and ‘1’.
Similarly, VIH and VIL are maximum and minimum input voltages, respectively, at logic level ‘1’
and ‘0’.
Figure 5(a) shows that the slopes of VTC curve are very large between VIL and VIH . For better
noise immunity in any inverter circuit, slope of the VTC curve should be steep and desired
condition is NMH ¼ NML ¼ Vdd =2: The result obtained from figure shows that the NML is 0.6 V
and NMH is 0.7 V; hence, very near to Vdd =2.
The transient and DC analyses of the proposed TBRS FD-SOI MOS structure-based CMOS inverter
circuit are very promising and therefore applied to the design of 6T SRAM cell. The static noise
margin (SNM) is considered as a stability of any SRAM cell, which is defined as the highest DC
margin for which the cell state does not flip during its access. SNM of a bit cell is derived from
butterfly curve. Figure 9 shows the butterfly curve of SRAM cell which corresponds to an ideal
circuit. The read SNM from both transfer characteristics is extracted by a square-fitting method that
is the largest square to be fitted in between overlapped plot of inverter transfer characteristics and
its inverse characteristics. The SNM of the proposed cell is obtained as 565 mV which is much
better than any other cell designed at 50 nm gate length MOS device.
The performance comparison between the proposed structure and various field effect transistors (FET's) (JLT, Tunnel FET and SOI FET etc.) structures are shown in Table 3. The result shows that
compared to any other device reported in literature, the proposed structure at low dimension
(50 nm gate length) has better electrical performance so far at this technology node. The switching
SNM
1.6
1.4
1.2
1
Vin/Vout
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7. CMOS circuit used as a SRAM high-density ICs
0.8
VOUT
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Vin/Vout
Figure 9. Static transfer characteristic curve of proposed inverter circuit which shows the SNM is 565 mV.
1.6
INTERNATIONAL JOURNAL OF ELECTRONICS
85
Table 3. Performance comparison of various tunnel-based MOSFET, SOI MOSFET and JLT (as reported in the literature) with that
of proposed TBRS FD-SOI MOSFET.
References
FD-SOI (Yeh et al., 2015)
SOI FinFET (Saremi et al.,
2012)
TDBC (J. Chen et al., 2011)
PNPN (Nagavarapu, Member,
Jhaveri, & Woo, 2008)
Tunnel FET (Khatami &
Banerjee, 2009)
SOI MOSFET (Anvarifard,
Member, & Orouji, 2013)
Channel
length
Sub-threshold
slope
Ion/
Ioff
60 mv/decade
78.16 mv/
decade
10 pA 0.4 V 1.8 nm 68 mv/decade
10 nA 0.3 V
25A <60 mv/
decade
10 fA 0.13 V
–
15 mv/decade
108
108
10 pA 0.4 V
1.3 nm 66 mv/decade
108
10 mA 100 pA 0.5 V
10 mA 10 pA 0.3 V
1.3 nm 94 mv/decade
–
80 mv/decade
107
108
10 mA
3 mA
1.2 nm –
1 nm 60 mv/decade
106
1010
Ion
50 nm
50 nm
1V
1V
130 nm
100 nm
1.2 V
1.1 V
1 mA
1 mA
Lch = 70 nm 0.6 V
LSiGe = 3 nm
Lg = 200 nm 0.9 V
1 uA
Lg = 30 nm
SCE SOI (Anvarifard & Orouji, 20 nm
2013)
JLT (Sahu & Singh, 2014)
18 nm
Proposed work
50 nm
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Vds
0.9 V
1.0 V
Vsub = −5 V
1.0
1.0 V and
scaled 0.4 V
Ioff
Vth
Tox
0.1 mA 1 pA 0.3 V
1 mA 10 pA 0.272
10 mA
1 nA
80 fA
0.3 V
0.3 V
1 nm
2 nm
108
109
109
Table 4. Performance comparisons of various CMOS circuits reported with the proposed CMOS circuit.
References
JLT (Sahu & Singh, 2014)
Tunnel FET
(J. Chen et al., 2011)
CMOS (Jung, Katz, & Andreou, 2010)
SOI CMOS
(Zhang, Han, Lin, Wu, & Chan, 2004)
This work
This work
Ion/Ioff
106
109
Vm
–
0.5V
SNM
140 mv
–
Delay
3.7 ps
20 ps
40 nm
130 nm
–
105
–
–
415 mv
~40 ps
50 nm
200 nm
1010
106
0.5 V
0.3 V
565 mv
–
0.2 ps
20 ns
Channel length
18 nm
Lch = 70 nm LSiGe = 3 nm
ratio (Ion to Ioff ratio) should be high for the device and as per the result shown in the table, its
switching ratio is quite high compared to any other reported device.
The performance comparison between the proposed structure-based CMOS structure and
various FET-based (JLT, Tunnel FET, SOI FET, etc.) CMOS circuits are shown in Table 4. The result
shows that the CMOS circuit based on our transistor at 50 nm gate length has low delay, desired
threshold voltage (Vm) and high NM compared to any other device reported. The switching of
CMOS circuit is quite high compared to any other CMOS inverter circuit reported so far. The result
shows that at lower dimension, the performance of proposed device and CMOS inverter circuit
shows better performance compared to reported literature.
Hence, the performance of proposed inverter is a good compromise between its speed and
power consumption.
8. Conclusions
In this work, a novel area-efficient layout of CMOS circuit has been designed and simulated at
50 nm gate length using Sentaurus device simulator. The area consumed is much less than the
conventional FD-SOI CMOS circuits. The proposed MOS device structure exhibits lower sub-threshold slope, lower Ioff current and higher Ion to Ioff ratio when compared to FD-SOI and SOI FinFET
devices. It was found that the proposed CMOS circuit shows improvement in delay time, desired
threshold voltage (Vm) and NM compared to any other available CMOS circuits. Thereafter, the
proposed device design layout was used to form the 6-T SRAM cell and study its electrical
performances. The SNM of the proposed SRAM cell was found to be 565 mV, which is much better
than the SNM of any other 6-T SRAM cell designed using 50 nm gate length MOS technology. The
86
V. K. MISHRA AND R. K. CHAUHAN
study therefore indicates that such efficient layout design shall be useful in the design of highdensity ICs.
Acknowledgement
This work was supported by the AICTE under research promotion scheme (RPS-60). Authors would like to thank IIT
Kanpur and IIT Indore for providing Sentaurus tool in their VLSI/EDA lab.
Disclosure statement
No potential conflict of interest was reported by the authors.
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Funding
This work was supported by the AICTE under research promotion scheme [RPS-60].
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