eGaN® FET DATASHEET
EPC8010
EPC8010 – Enhancement Mode Power Transistor
VDS , 100 V
RDS(on) , 160 mW
ID , 2.7 A
New Product
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device
structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial as
well as those where on-state losses dominate.
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (LiDAR)
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
Maximum Ratings
VDS
ID
VGS
TJ
TSTG
Drain-to-Source Voltage (Continuous)
100
Continuous (TA = 25˚C, RθJA = 57˚C/W)
2.7
Pulsed (25˚C, TPulse = 300 µs)
7.5
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
Operating Temperature
-40 to 150
Storage Temperature
-40 to 150
EPC8010 eGaN FETs are supplied only in
passivated die form with solder bars
V
A
V
˚C
Static Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
BVDSS
IDSS
IGSS
VGS(TH)
TEST CONDITIONS
MIN
Drain-to-Source Voltage
VGS = 0 V, ID = 125 µA
100
TYP
MAX
UNIT
V
Drain Source Leakage
VGS = 0 V, VDS = 80 V
20
100
Gate-to-Source Forward Leakage
VGS = 5 V
0.1
0.5
µA
mA
Gate-to-Source Reverse Leakage
VGS = -4 V
20
100
µA
1.4
2.5
V
160
mΩ
Gate Threshold Voltage
VDS = VGS, ID = 0.25 mA
0.8
RDS(on)
Drain-Source On Resistance
VGS = 5 V, ID = 0.5 A
120
VSD
Source-Drain Forward Voltage
IS = 0.5 A, VGS = 0 V
2.5
V
Specifications are with substrate shorted to source where applicable.
Thermal Characteristics
TYP
UNIT
RθJC
Thermal Resistance, Junction to Case
8.2
˚C/W
RθJB
Thermal Resistance, Junction to Board
16
˚C/W
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
82
˚C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 1
eGaN® FET DATASHEET
EPC8010
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
43
55
25
36
0.5
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
0.3
RG
Gate Resistance
0.3
QG
Total Gate Charge
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
VDS = 50 V, VGS = 0 V
VDS = 50 V, VGS = 5 V, ID = 1 A
UNIT
pF
Ω
360
480
130
VDS = 50 V, ID = 1 A
60
100
pC
100
VDS = 50 V, VGS = 0 V
3300
2200
0
Specifications are with substrate shorted to source where applicable.
Figure 2: Transfer Characteristics
Figure 1: Typical Output Characteristics at 25°C
7
7
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
5
VDS = 3 V
4
3
5
4
3
2
2
1
1
0
0
0.5
1.0
1.5
2.0
2.5
VDS – Drain-to-Source Voltage (V)
25˚C
125˚C
6
ID – Drain Current (A)
ID – Drain Current (A)
6
0
3.0
0.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
500
ID = 0.5 A
ID = 1 A
ID = 1.5 A
ID = 2 A
400
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
1.5
Figure 4: RDS(on) vs. VGS for Various Temperatures
Figure 3: RDS(on) vs. VGS for Various Drain Currents
500
300
200
100
0
1.0
2.5
3.0
3.5
4.0
4.5
5.0
25˚C
125˚C
400
ID = 1 A
300
200
100
0
2.5
3.0
VGS – Gate-to-Source Voltage (V)
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
3.5
4.0
4.5
5.0
VGS – Gate-to-Source Voltage (V)
| PAGE 2
eGaN® FET DATASHEET
EPC8010
Figure 5b: Capacitance (Log Scale)
Figure 5a: Capacitance (Linear Scale)
100
80
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
Capacitance (pF)
60
40
10
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1
20
0
0
20
40
60
VDS – Drain-to-Source Voltage (V)
80
0.1
100
0
Figure 6: Gate Charge
40
60
VDS – Drain-to-Source Voltage (V)
80
100
Figure 7: Reverse Drain-Source Characteristics
5
8
4
25˚C
125˚C
7
ID = 1 A
VDS = 50 V
ISD– Source-to-Drain Current (A)
VGS – Gate-to-Source Voltage (V)
20
3
2
1
6
5
4
3
2
1
Normalized On-State Resistance - RDS(on)
2.0
1.8
0
0.1
0.2
QG – Gate Charge (nC)
0.3
Figure 8: Normalized On-State Resistance vs. Temperature
1.4
ID = 1 A
VGS = 5 V
1.3
1.6
1.4
1.2
1.0
0.8
0
0
0.4
Normalized Threshold Voltage (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VSD– Source-to-Drain Voltage (V)
4.5
5.0
Figure 9: Normalized Threshold Voltage vs. Temperature
ID = 0.25 mA
1.2
1.1
1.0
0.9
0.8
0.7
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
0.6
0
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
25
50
75
100
TJ – Junction Temperature (°C)
125
150
| PAGE 3
eGaN® FET DATASHEET
EPC8010
Figure 10: Gate Leakage Current
Figure 11: Smith Chart
1.2
1.0
1.4
1.2
0.5
2.0
1.8
0.6
1.6
0.7
0.8
0.8
0.9
1.0
3.
0.6
0
S11 – Gate Reflection
S22 – Drain Reflection
EPC8010
0.4
0.3
4.0
5.0
0.2
0.4
6.0
8.0
10
3 GHz
0.1
10
3.0
5.0
4.0
1.8
2.0
1.6
1.2
1.4
1.0
0.9
20
0.2
0.1
8.0
10
0.2
200 MHz
5.0
RF Café
2002
4.0
0.3
5
6
0
4
3.
3
0.4
2.0
2
VGS – Gate-to-Source Voltage (V)
1.8
1
1.6
1.4
1.2
1.0
0.9
0.8
0.7
0.6
0
0.5
0
0.8
0.7
0.6
0.5
0.4
0.2
0.3
0
0.1
20
6.0
IG – Gate Current (mA)
S-Parameter Characteristics
VGSQ = 1.34 V, VDSQ = 50 V, IDQ = 0.50 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
25˚C
125˚C
All measurements were done with substrate shortened to source.
Figure 13: Device Reflection
Figure 12: Gain Chart
Amplitude [dB]
25˚C
125˚C
1.0
0.8
EPC8010
20
0.6
15
0.4
10
0.2
5
0
Frequency (MHz)
–.0.2
1000
Z GS
Figure 14: Taper and Reference Plane details – Device Connection
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
Frequency
Gate (ZGS)
Drain (ZDS)
[MHz]
[Ω]
[Ω]
200
2.54 – j11.18
22.54 – j23.91
500
1.57 – j4.20
6.01 – j15.53
1000
0.94 – j0.23
1.85 – j6.89
1200
0.97 + j0.89
1.47 – j4.87
1500
0.97 + j2.38
1.51 – j2.52
2000
1.08 + j4.80
2.09 + j0.41
2400
1.21 + j6.74
2.50 + j2.25
3000
1.62 + j10.34
3.05 + j5.00
S-Parameter Table - Download S-parameter files at www.epc-co.com
914
355
All dimensions in µm
914
1621
0
100
Z DS
271
25
1.2
Gmax
271
35
1.4
1621
40
30
1.6
1000
45
Device Outline
Gate Circuit
Reference Plane
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149
Drain Circuit
Reference Plane
| PAGE 4
eGaN® FET DATASHEET
EPC8010
Figure 15: Transient Thermal Response Curves
Junction-to-Board
ZθJB Normalized Thermal Impedance
1
Duty Factors:
0.5
0.2
0.1
0.1
0.05
T
0.02
0.01 0.01
P DM
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
0.001
10-5
tp
10-4
10-3
10-2
10-1
1
10+1
tp– Rectangular Pulse Durationn, seconds
ZθJC Normalized Thermal Impedance
1
Junction-to-Case
Duty Factors:
0.5
0.1
0.2
0.1
0.05
T
P DM
0.02
0.01 0.01
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.001
10-6
tp
10-5
10-4
10-3
10-2
10-1
1
tp– Rectangular Pulse Durationn, seconds
Figure 16: Safe Operating Area
ID - Drain Current (A)
10
Limited by RDS(on)
1
Pulse Width
100 ms
10 ms
1 ms
100 µs
10 µs
TJ = Max Rated, TC =
+25°C, Single Pulse
0.1
TAPE AND REEL CONFIGURATION
d
b
4mm pitch, 8mm wide tape on 7” reel
10
VDS – Drain Voltage (V)
e
f
100
g
c
a
Gate Pad
bump is
under this
edge of die
Loaded Tape Feed Direction
YYYY
7” reel
1
ZZZZ
0.1
8010
Die is placed into pocket
bump side down
(face side down)
EPC8010 (Note 1)
Dimension (mm) target
a
8
1.75
b
c (see note 2)
3.5
d
4
e
4
f (see note 2)
2
g
1.5
min
7.9
1.65
3.45
3.9
3.9
1.95
1.5
max
8.3
1.85
3.55
4.1
4.1
2.05
1.6
Die
orientation
dot
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 5
eGaN® FET DATASHEET
EPC8010
DIE MARKINGS
8010
YYYY
ZZZZ
Die orientation dot
Laser Markings
Part
Number
EPC8010
Gate Pad bump is
under this edge of die
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
8010
YYYY
ZZZZ
DIE OUTLINE
Solder Bar View
A
d
e
e
1
i
X2
f
5
2
j
C
B
3
Dim
4
g
x2
6
h
i
All dimensions in µm
815 Max
(685)
RECOMMENDED
LAND PATTERN
600
225
2080
B
820
850
880
C
555
580
605
D
400
400
400
E
600
600
600
F
200
225
250
G
175
200
225
H
425
450
475
I
175
200
225
J
400
400
400
6
2
400
560
850
180
X2
600
4
180
x2
2050
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
2050
1
Max
2020
100 +/- 20
SEATING PLANE
400
Nominal
A
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
Side View
(units in µm)
Micrometers
Min
3
5
430
180
The land pattern is solder mask defined.
Solder mask opening is 10 µm smaller per side than bump.
All dimensions in µm
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
Information subject to
change without notice.
Revised January, 2015
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 6