eGaN® FET DATASHEET
EPC8002
EPC8002 – Enhancement Mode Power Transistor
VDS , 65 V
RDS(on) , 480 m
ID , 2 A
New Product
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device
structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial as
well as those where on-state losses dominate.
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (LiDAR)
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
Maximum Ratings
VDS
ID
VGS
TJ
TSTG
Drain-to-Source Voltage (Continuous)
65
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150° C)
78
Continuous (TA = 25˚C, RθJA= 37 ˚C/W)
2
Pulsed (25˚C, TPulse = 300 µs)
2
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
Operating Temperature
-40 to 150
Storage Temperature
-40 to 150
PARAMETER
EPC8002 eGaN FETs are supplied only in
passivated die form with solder bars
Die Size: 2.1 mm x 0.85 mm
V
A
V
˚C
www.epc-co.com/epc/Products/eGaNFETs/EPC8002.aspx
TEST CONDITIONS
MIN
65
TYP
MAX
UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 125 µA
IDSS
Drain Source Leakage
VDS = 52 V, VGS = 0 V
20
100
µA
Gate-to-Source Forward Leakage
VGS = 5 V
0.1
1
mA
Gate-to-Source Reverse Leakage
VGS = –4 V
20
100
µA
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 0.1 mA
1.4
2.5
V
RDS(ON)
Drain-Source On Resistance
VGS = 5 V, ID = 0.5 A
380
480
mΩ
VSD
Source-Drain Forward Voltage
IS = 0.4 A, VGS = 0 V
2.6
IGSS
0.8
V
V
Specifications are with substrate shorted to source where applicable.
Thermal Characteristics
TYP
UNIT
RθJC
Thermal Resistance, Junction to Case
8.2
˚C/W
RθJB
Thermal Resistance, Junction to Board
16
˚C/W
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
82
˚C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 1
eGaN® FET DATASHEET
EPC8002
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
24
0.12
0.18
6.7
10
UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
VDS = 32.5 V, VGS = 0 V
Effective Output Capacitance,
Energy Related (Note 2)
Effective Output Capacitance,
Time Related (Note 3)
COSS(ER)
COSS(TR)
RG
Gate Resistance
QG
Total Gate Charge
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
pF
8.9
VDS = 0 to 32.5 V, VGS = 0 V
10
Ω
0.3
133
VDS = 32.5 V, VGS = 5 V, ID = 0.5 A
167
57
VDS = 32.5 V, ID = 0.5 A
15
26
pC
46
VDS = 32.5 V, VGS = 0 V
500
334
0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
2.0
2.0
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
V DS = 3 V
1.5
ID– Drain Current (A)
ID– Drain Current (A)
1.5
25˚C
125˚C
1.0
1.0
0.5
0.5
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
3.0
1.0
1.5
Figure 3: RDS(on) vs VGS for Various Drain Currents
3.0
3.5
4.0
4.5
5.0
Figure 4: RDS(on) vs VGS for Various Temperatures
1500
RDS(on) – Drain-to-Source Resistance (mΩ)
1500
RDS(on)– Drain-to-Source Resistance (mΩ)
2.5
VGS– Gate-to-Source Voltage (V)
VDS– Drain-to-Source Voltage (V)
ID= 0.5 A
1200
ID= 1.0 A
ID= 1.5 A
ID= 2.0 A
900
600
300
0
2.5
2.0
3.0
3.5
4.0
4.5
5.0
25˚C
125˚C
1200
ID = 0.5 A
900
600
300
0
2.5
3.0
VGS– Gate-to-Source Voltage (V)
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
3.5
4.0
4.5
5.0
VGS – Gate-to-Source Voltage (V)
| PAGE 2
eGaN® FET DATASHEET
EPC8002
Figure 5A: Capacitance (Log Scale)
Figure 5: Capacitance (Linear Scale)
100
25
10
C – Capacitance (pF)
C – Capacitance (pF)
20
COSS = CGD + CSD
CISS = CGD + CGS
15
CRSS = CGD
10
COSS = CGD + CSD
CISS = CGD + CGS
1
CRSS = CGD
0.1
5
0
0
10
20
30
40
50
0.01
60
0
10
20
ID= 0.5 A
VDS = 32.5 V
4
3
2
1
0
0.05
0.1
1.0
0.5
0
0.15
25˚C
125˚C
1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VSD – Source-to-Drain Voltage (V)
QG– Gate Charge (nC)
Figure 9: Normalized Threshold Voltage vs Temperature
Figure 8: Normalized On-State Resistance vs Temperature
1.4
2.2
ID = 0.5 A
VGS = 5 V
ID = 0.1 mA
1.3
Normalized Threshold Voltage (V)
Normalized On-State Resistance – RDS(on)
60
2.0
ISD – Source-to-Drain Current (A)
VGS – Gate-to-Source Voltage (V)
5
1.8
1.6
1.4
1.2
1.0
0.8
50
Figure 7: Reverse Drain-Source Characteristics
Figure 6: Gate Charge
2.0
40
VDS– Drain-to-Source Voltage (V)
VDS– Drain-to-Source Voltage (V)
0
30
1.2
1.1
1.0
0.9
0.8
0.7
0
25
50
75
100
125
150
0.6
0
25
TJ – Junction Temperature (°C)
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
50
75
100
125
150
TJ– Junction Temperature (°C)
| PAGE 3
eGaN® FET DATASHEET
EPC8002
Figure 10: Gate Leakage Current
Figure 11: Smith Chart
0.30
1.0
1.4
1.2
0.4
3.
0
S11 – Gate Reflection
S22 – Drain Reflection
0.5
0.15
2.0
1.8
0.6
1.6
0.7
0.8
0.20
0.9
25˚C
125˚C
0.25
0.3
4.0
5.0
0.2
0.10
6.0
8.0
10
0.1
IG – Gate Current (mA)
S-Parameter Characteristics
VGSQ = 1.17 V, VDSQ = 30 V, IDQ = 0.2 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
0.05
10
3.0
5.0
4.0
1.8
2.0
1.6
1.2
1.4
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.2
0.3
0
0.1
20
20
0.1
8.0
10
6.0
0.2
5.0
RF Café
2002
0.3
6
0
5
3.
4
0.4
1.6
1.4
0.7
0.6
1.8
2.0
0.5
VGS – Gate-to-Source Voltage (V)
1.2
3
1.0
2
0.9
1
0.8
0
4.0
0
All measurements were done with substrate shortened to source.
Figure 13: Device Reflection
Figure 12: Gain Chart
45
1.6
1.4
Gmax
35
1.2
30
1.0
25
0.8
20
0.6
15
0.4
10
0.2
5
0
Figure 14: Taper and Reference Plane details – Device Connection
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
Gate (ZGS)
Drain (ZDS)
[MHz]
[Ω]
[Ω]
200
3.09 - j29.97
63.13 - j71.32
500
2.20 - j11.92
15.96 -j46.65
1000
1.14 - j4.46
3.35 - j23.47
1200
0.95 - j2.76
1.91 - j18.52
1500
0.87 - j0.55
1.66 - j12.66
2000
1.09 + j2.61
2.28 - j6.12
2400
1.44 + j4.87
4.35 - j2.80
3000
2.36 + j8.79
6.41 + j0.69
S-Parameter Table - Download S-parameter files at www.epc-co.com
914
355
All dimensions in µm
914
1621
Frequency
271
Frequency (MHz)
-0.2
1000
271
100
Z GS
1621
0
Z DS
1000
Amplitude (dB)
40
Device Outline
Gate Circuit
Reference Plane
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149
Drain Circuit
Reference Plane
| PAGE 4
eGaN® FET DATASHEET
EPC8002
1
0.1
Figure 16: Safe Operating Area
Junction-to-Board
Duty Factors:
0.5
0.2
0.1
0.05
1
T
0.02
0.01 0.01
P DM
0.001
10-5
tp
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
10-4
10-3
10-2
10-1
1
Limited by RDS(on)
ID - Drain Current (A)
ZθJB Normalized Thermal Impedance
Figure 15: Transient Thermal Response Curves
10
Pulse Width
100 ms
10 ms
1 ms
100 µs
10 µs
tp– Rectangular Pulse Duration (s)
Junction-to-Case
ZθJC Normalized Thermal Impedance
1
0.1
0.1
Duty Factors:
0.5
0.1
1
10
VDS – Drain Voltage (V)
100
0.2
0.1
0.05
T
P DM
0.02
0.01 0.01
Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
0.001
10-5
tp
10-4
10-3
10-2
10-1
1
10
tp– Rectangular Pulse Duration (s)
d
b
a
7” reel
f
Gate Pad
bump is
under this
edge of die
Loaded Tape Feed Direction
g
c
YYYY
4mm pitch, 8mm wide tape on 7” reel
e
ZZZZ
TAPE AND REEL CONFIGURATION
8002
Die is placed into pocket
bump side down
(face side down)
EPC8002 (Note 1)
Dimension (mm) target min
a
8
7.9
1.75 1.65
b
c (see note 2)
3.5 3.45
d
4
3.9
e
4
3.9
f (see note 2)
2
1.95
g
1.5
1.5
max
8.3
1.85
3.55
4.1
4.1
2.05
1.6
Die
orientation
dot
Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
8002
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this edge of die
Part
Number
EPC8002
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
8002
YYYY
ZZZZ
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 5
eGaN® FET DATASHEET
EPC8002
DIE OUTLINE
A
Solder Bar View
d
e
e
i
X2
2
4
g
x2
6
h
i
Micrometers
Min
Nominal
Max
A
2020
2050
2080
B
820
850
880
C
555
580
605
D
400
400
400
E
600
600
600
F
200
225
250
G
175
200
225
H
425
450
475
I
175
200
225
J
400
400
400
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
100 +/- 20
(685)
Side View
(units in µm)
SEATING PLANE
RECOMMENDED
LAND PATTERN
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate
2050
(units in µm)
400
600
600
6
400
2
3
190
190
1
570
4
850
815 Max
5
j
1
C
B
3
Dim
f
The land pattern is solder mask defined.
5
190
440
RECOMMENDED
STENCIL DRAWING
(units in µm)
Recommended stencil should be 4 mil (100 μm) thick, must be laser
cut, openings per drawing.
Additional assembly resources available at:
http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
850
272
Intended for use with SAC305 Type 3 solder, reference 88.5% metals
content.
200
592
200
250
2050
R 60
325
200
245
230
450
275
272
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
Information subject to
change without notice.
Revised November, 2015
| PAGE 6