eGaN® FET DATASHEET
EPC2025
EPC2025 – Enhancement Mode Power Transistor
VDSS , 300 V
RDS(on) , 120 m
ID , 6.3 A
NEW PRODUCT
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s
exceptionally high electron mobility allows very low RDS(on), while its lateral device structure and
majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.
EPC2025 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 1.95 mm x 1.95 mm
Maximum Ratings
VDS
ID
VGS
TJ
TSTG
Drain-to-Source Voltage (Continuous)
300
Continuous (TA = 25˚C, RΘJA = 13˚C/W)
6.3
Pulsed (25˚C, TPULSE = 300 µs)
20
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
Operating Temperature
-40 to 150
Storage Temperature
-40 to 150
Applications
• Ultra High Frequency DC-DC conversion
• Medical
• Solar
• LED Lighting
V
A
Benefits
• Ultra High Efficiency
• Ultra Low Switching and Conduction Losses
• Zero QRR
• Ultra small footprint
V
˚C
www.epc-co.com/epc/Products/eGaNFETs/EPC2025.aspx
Static Characteristics (TJ = 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
300
TYP
MAX
UNIT
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 120 µA
IDSS
Drain Source Leakage
VDS = 240 V, VGS = 0 V
20
100
µA
Gate-to-Source Forward Leakage
VGS = 5 V
0.1
2
IGSS
Gate-to-Source Reverse Leakage
VGS = -4 V
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 1 mA
RDS(on)
VSD
Drain-Source On Resistance
Source-Drain Forward Voltage
0.8
VGS = 5 V, ID = 3 A
IS = 0.5 A, VGS = 0 V
V
20
100
mA
µA
1.4
2.5
V
90
120
m
V
2.5
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
UNIT
RΘJC
Thermal Resistance, Junction to Case
1.6
˚C/W
RΘJB
Thermal Resistance, Junction to Board
9.5
˚C/W
RΘJA
Thermal Resistance, Junction to Ambient (Note 1)
64
˚C/W
Note 1: RΘJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 1
eGaN® FET DATASHEET
EPC2025
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
200
240
CISS
Input Capacitance
CRSS
Reverse Transfer Capacitance
COSS
Output Capacitance
46
COSS(ER)
Effective Output Capacitance
Energy Related (Note 2)
64
COSS(TR)
Effective Output Capacitance
Energy Related (Note 3)
RG
Gate Resistance
QG
Total Gate Charge
UNIT
0.1
VDS = 240 V, VGS = 0 V
70
pF
VDS = 0 to 240 V, VGS = 0 V
93
0.3
VDS = 240 V, VGS = 5 V, ID = 3 A
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
Ω
1.8
2.3
0.72
VDS = 240 V, ID = 3 A
0.32
0.54
nC
0.54
VDS = 240 V, VGS = 0 V
22
33
0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 80% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 80% BVDSS.
Figure 2: Transfer Characteristics
Figure 1: Typical Output Characteristics at 25°C
20
20
15
ID – Drain Current (A)
15
ID – Drain Current (A)
25°C
125°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
10
5
0
10
5
0
1
2
3
4
5
VDS – Drain-to-Source Voltage (V)
0
6
ID = 2 A
ID = 3 A
ID = 4 A
ID = 6 A
240
160
80
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 4: RDS(on) vs VGS for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
320
0.5
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs VGS for Various Drain Currents
0
VDS = 6 V
4.5
5.0
320
25°C
125°C
ID = 3 A
240
160
80
0
2.5
3.0
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
| PAGE 2
eGaN® FET DATASHEET
EPC2025
Figure 5a: Capacitance (Linear Scale)
Figure 5b: Capacitance (Log Scale)
350
1000
300
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
Capacitance (pF)
Capacitance (pF)
250
200
150
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
10
1
100
0.1
50
0
0
50
100
150
200
250
VDS – Drain-to-Source Voltage (V)
0.01
300
ID = 3 A
VDS = 240 V
4
ISD – Source-to-Drain Current (A)
VGS – Gate-to-Source Voltage (V)
150
200
250
300
10
3
2
1
0
0.5
1.0
QG – Gate Charge (nC)
1.5
6
4
2
0
2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VSD – Source-to-Drain Voltage (V)
Figure 9: Normalized Threshold Voltage vs Temperature
1.4
2.0
1.3
1.8
1.6
ID = 3 A
VGS = 5 V
1.2
1.0
Normalized Threshold Voltage
2.2
1.4
25°C
125°C
8
Figure 8: Normalized On-State Resistance vs Temperature
Normalized On-State Resistance – RDS(on)
100
Figure 7: Reverse Drain-Source Characteristics
5
0.8
50
VDS – Drain-to-Source Voltage (V)
Figure 6: Gate Charge
0
0
ID = 1 mA
1.2
1.1
1.0
0.9
0.8
0.7
0
25
50
75
100
TJ – Junction Temperature (ºC)
125
150
0.6
0
25
50
75
100
TJ – Junction Temperature (ºC)
125
150
All measurements were done with substrate shortened to source.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 3
eGaN® FET DATASHEET
EPC2025
Figure 10: Gate Leakage Current
4
25°C
125°C
IG – Gate Current (mA)
3
2
1
0
0
1
2
3
4
5
6
VGS – Gate-to-Source Voltage (V)
Figure 11: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
1
0.1
0.01
Transient Thermal Response Curves (Junction-to-Board)
Duty Factors:
0.5
0.1
0.05
0.02
0.01
PDM
t1
Single Pulse
0.001
0.0001
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
10-5
10-4
10-3
10-2
10-1
1
10
tp, Rectangular Pulse Duration, seconds
0.5
Transient Thermal Response Curves (Junction-to-Case)
0.2
Duty Factors:
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
ZθJC, Normalized Thermal Impedance
1
0.1
0.05
0.02
0.01
Single Pulse
0.001
0.0001
PDM
t1
t2
Notes:
Single
Duty Factor:
D = tPulse
1/t2
Peak TJ = PDM x ZθJC x RθJC + TB
10-6
10-5
10-4
10-3
10-2
10-1
1
tp, Rectangular Pulse Duration, seconds
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 4
eGaN® FET DATASHEET
EPC2025
Figure 12: Safe Operating Area
ID – Drain Current (A)
10
Limited by RDS(on)
1
0.1
Pulse Width
100 ms
10 ms
1 ms
100 µs
0.1
1
10
100
VDS – Drain Voltage (V)
TAPE AND REEL CONFIGURATION
b
4mm pitch, 8mm wide tape on 7” reel
e
d
f
g
Loaded Tape Feed Direction
Gate pad bump
is under this
corner of die
7” reel
c
2025
YYYY
ZZZZ
a
Die orientation dot
Die is placed into pocket
solder bump side down
(face side down)
EPC2025 (note 1)
Dimension (mm) target min
a
b
c (see note)
d
e
f (see note)
g
8.00
1.75
3.50
4.00
4.00
2.00
1.5
7.90
1.65
3.45
3.90
3.90
1.95
1.5
max
8.30
1.85
3.55
4.10
4.10
2.05
1.6
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
Die orientation dot
2025
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
EPC2025
2025
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
YYYY
ZZZZ
Gate Pad bump is
under this corner of die
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 5
eGaN® FET DATASHEET
EPC2025
A
DIE OUTLINE
f
DIM
4
8
12
3
7
11
A
B
c
d
e
f
g
c
Solder Bump View
B
c
e
6
10
1
5
9
c
2
d
MAX
1920
1920
400
800
180
360
160
1950
1950
400
800
200
375
175
1980
1980
400
800
220
390
190
100 ± 20
(685)
Side View
SEATING PLANE
1950
The land pattern is solder mask defined
Solder mask is 5 μm smaller per side than bump
375
175
1
5
9
2
6
10
Pad 1 is Gate;
Pads 2, 3, 4, 9, 10, 12 are Source;
400
(measurements in µm)
Nominal
Pad 1 is Gate;
Pads 5, 6, 7, 8 are Drain;
Pads 2, 3, 4, 9, 10, 12 are Source;
Pad 11 is Substrate
d
RECOMMENDED
LAND PATTERN
MIN
(785)
g
Micrometers
6
Pad 11 is Substrate
11
400
3
Pads 5, 6, 7, 8 are Drain;
1950
400
190
4
8
12
800
800
RECOMMENDED
STENCIL DRAWING
Recommended stencil should be 4 mil (100 µm) thick, must
be laser cut, openings per drawing.
1950
R6
0
(measurements in µm)
400
Intended for use with SAC305 Type 3 solder, reference 88.5%
metals content.
1950
400
225
Additional assembly resources available at
http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
400
275
800
800
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
Information subject to
change without notice.
Revised November, 2015
| PAGE 6