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80G51familyarchitecture
80C51Family
80C5,IARCHITECTURE
MEMORYORGANIZATION
lor prcgram
All80c51devices
hav€s€parals
addrcss
spac€s
and
daiamemory,
as€hown
inFigulos
l snd2.Th€loglcalsopafatlon
or
progEmanddatamemory
allowslh€dalalliemorylo b€ac.6€s€d
whichcanbequicklysioedandmanipulaied
by
by8-biteddrosses,
16-bhdaiamemory
an8 bitcPU.Nev€rlh€l€ss,
addr6$ascanalso
begenehiedthoush the DP'IR€gisl6r.
€n onlyberead,nolwdtlento.
P@gEm'ie'nory(ROM,EPROM)
Therecanbe uplo 64kbytosof programmemoryIn the 80c51, the
lowesl4k b!,iesol progEmareon{hip, ln lh€ ROMI€ssvsrsions,all
prcg@nrrnemoryls exlemal.The Ead slrobelor exlemalprogran
memoryis tlreFSEN(prcgramsioe enabre).
DataMemory(RAr',4)
occuplesa separaleaddrcssspacerDm
PrcgEn Memoryln lh€ 80C51, ihe lowst 128byiesoi data
mgmoryae on-chip.Uplo 64kbyt€sot oxt€malMl', can be
DataMemorv
sDa@.Inlhe ROMless
addre66ed
inlh€exiernal
ThecPU generales
read
veBiof,lhelowest128bylesareon-chip.
dunngexlernal
Data
andwdtesignals,
RDandWR,asneeded
Exl€mslProgEmMemoryandsxlomalDalal'rsmorymayb€
combinedif desied by applyingthe ROand PSENsignslsto th6
inputsof anANDeateandusingthe oulputof lh€ gal€ asth€ read
s1rcb6lo lhe sxlemaiPDgEm/Datamehory
ProgramMemoty
Fieue 3 showsa mapol th€ loworparl of the PbgEm Memory
fromlocation
0000H.4s
After€ser,rheCPUbeginsexeculion
is assigned
a nxedlo€tionin
3, eachint€rrupt
shdn in Figure
ProgEm[4emory
TheinlsnupicausesthecPu lojumplo thal
execuiionoi the *ryi@ Eut ne,
lo6iion. wh€r€it commences
!o location
0003H,lf
Extemal
Inlerupl0,ioretample,is assigned
ExGmalIntempl0 is golngto be used,its seruicerculinemust
beginal location0003H,It the Interrupiis notgoinglo be uBed,its
PogEmMemory
i! available
asgeneElpurpose
sewicelocation
The Inb|nipt s€Nicelocationsarespacedar 8-b!,1eintetuals:0003H
ior Enemal
forE{6mal'nterruot
0,0008HiorTlmer0,0013H
Interupi1,0018Hior]lmer1, etc.lf an interupt€ewic€routine
i5
shodonolqhiasisonenihe cas6l. co.aolappli€tlons)itcan
resideenli.elywjhin
thal&by4einleryal.
Longer
seryie.outi.es
to skipoversubs€quenlinl€rupt
€n useajumpinslruclion
locqlions,lfothor
inl6nupls
af€in us6.
Th6lowesl4k btiss ot Prog€n Memoryc€nsitherbo in lh€ on-chip
ROMorin anexiemalRO[l.
Thisselectior
is madebystappingthe
g (E{omalAccess)
pinto eiiherVcc,orVss.lnihe80C51,
!iihe
E pin s siEppedio Vcc, thenihe progEmietchesto addrcsses
0000Hlhrough
oFFFHaredieciedlo theintemalROM.
Progmm
FFFFHaredirecled
lo exlernal
felchos
to add€ss€s1000Hthrough
ROM.
10Vss,thenallpbobm ietches
are
flh6m pinis slrapp6d
pads(8031,80C31,
diectedio exienalROM.
TheROMles6
etc,)
lo
muslhaveihispinenemaltslrapp€d
lo Vsslo 6.abl6lh6m
€x6cut€frornexlomalProqrarnliernory.
Th6r€ad€lrobelo ext€nal ROtl, PSEN,is usedfiI all extehal
prcqramierches.PSENis noractivaredior intemalprcgramielches.
ThehardwareconnguEiionfor externalprogEmexe@lionis shown
in Figure
4. Notelhai 16l/Olines(Pods0 and2) ar€d€dicBt€d
b
durlngextemalPrcgram
Memoryfetches.
Port0 (P0
bustu.ctions
lho
InFigure
4) seruesasa multiplexed
addre66/dala
bus.11€ftits
lowbyteof lho Prcg€mCount€r(PCL)as an address,andthen
goesIntoa foai siateawaitingtheam'valof lhe codebtle ftomthe
Program[,lemoryDur'nglhe timethai the low byteol lhe Prcg€m
counleris validon Porl 0, lh€ 6ignalALE{Add6ssLatch€nable)
Pon2 (P2in
clock8
lhisby4sinloan add€sslabn.Meanwhile,
FiCUre
4)emitsihehighbtle otihePrcgFmCourtff(PCH).Ihen
FSENsiobes ihe EPROMandlh6 cod6b!,leis readinlolhe
Pog€m l4emory
address€s
ar€always16biiswide,evenihough
the aciualamountoi Pmg€m l\,4omory
usedmaybe less&an 64k
by[es.Enemalprcg€rnoxeculonsacrlflcesirc oflhe 8-bt pons,
Memory
P0andP2,lolhetunctonof addre$ingihePrcgram
Figurel. 80c51BlockDiagram
;
80C51familyarchitecture
80C51Family
ftlgEmMsmo'y
(RBd oirY)
Figur.2. 80C51MomorystNcture
I
)
Figurc3. 80C51Prosramlvl.mory
DataMemory
ThedohthafoiFiquc 2 sFodstheinlenalardextemalDai6
lo R|€80C51user'Flgure5 shMBa
availsble
Mem; sDac€s
for.ccsssilgupto 2kbvleso'6'lernal
hedw;r€conliou6tion
Pod0
int6malROM
inll'lsc5s€is€x€{'uling'om
RAM.TheCPU
3
lln6 ol
and
RAM,
bus
lo
the
addtesvdaia
seN6sas a multipl€xed
;;n t ar€benq ;seo !c passlhe RAlvlThe cPU s€n€ratBRD
dudngex[e'nalRAMsccssgs Th6r€
anoWRsio.alsasneed€d
ExrenalDal6
cdnbeuoio 64hb!'ieso'€nendOala Memory'
March1995
Figu.e 4. Ex€cutingItom Exl.rnal ProgEm MEmory
canb€€ilher1or2 bvl€swid€Onebvl€ '/o
M€troryaddess66
$ithoneo' moreoth€adde;es areoftenusedin conjunclion
lin€sto pagslhe RAM,as shownin Flgure5
Trc-btte add€ssesc€nalso be used'in whichcaselhe high
addE$ b)'teiEomited al Polt 2.
Fappedif Figur€6 Thet€-ory spa€ i5
lrteaa' DalsMemoryis
inloti€e blockswl'rcnae ger€Etvr€lercdtoas
shdn oivio€d
andSFRspace'
iheLow$128,thoUpper128,
80C51Family
InlemalDalaMemoryadd€ssesa.e alwaysonebytewld€,which
impllqsan addrossspac6oi only256 byias,How€v€r,
ihe
addressing
mod$ for intemalRAMcanin lacl ac@omodale384
bti€6,usinga simpl€
lrick,Di6cladd€sseshigherthan
7FH
accs on€dernoryBpae,andindirectaddBeshigherihan
7FH
accs a diferenimemoryspae. ThusFigure6 showsth6 Upper
128andSFRspa@occupyin!
ihesameblo6koi addresses,
80H
throlgh FFH,alihouohlhsy are physicallys€paralg6nt;ti63.
TheLowe'128bylesof RAI'Iarepresertinal.80C5'devi@s
as
mapped
in Figue7.Theldesl32 by,isarcgrouped
inlc4 lanks
oi 8 reglsteB.Prog€mInsiruollons
callout th6sefsglslsrsas R0
throughR7.Twobiis in ihe PbgramStaiusWord(PSW)s€lecl
whlcheglster bankis in u*. Thisallowsmoreefiiclenlus€of cod6
spa@,eince€gist€r imlructiomar€ shodsrthar inslruclionsthat
80C51familvarchitecture
Ths isxt 16by4s abovelhe rcgisterbanksfom a blockof
bil€ddessable
nemorvsDace.
Th€80C51inslruclion
6elincludes
a wideseleclio.of slnOl€-bh
inslructons,andth€ 128bilsin thls
a€a canbs di€cly addrssd by ih$e imtruclions-Thebii
addr6ss6s
Inlhisar€aa€ 00Hlhrcugh7FH.
All oi lhs b't€s i. lh€ Low€r128@n be accessedby eilherdiecl or
indiectaddressing.
TheUppe.l28(Flguls8) canonlyb6accesd
Flgure9 glvesa bd€tlookat lh6 SpecialFunclionResistq(SFR)
spac€,SFR6include
lhePortlatches,
timeB,pedpheral
conibls,
etc.TheseregisieBen only be accessedby dlEct addresslng.
Sixt€€naddressesin SFRspaceare boihbyte-andbiladdressabl€.
Thebi-addlBable SFRSae trlGe who* addressondsin 0Hor 8H,
Rl"
"{
Fisure5. Acc€3ing ExtemalDatsllemory
rthePrcg€m Memoryk Intemal,
ih€ Oth.r Blts of P2Ars Avall.ble as UO
Flgur€€, IntemalDataMemory
Fisurc 7. Lower'128By'* of Intemal RAtl
Figure8. Upp€r128Bytesof IniemalRAM
March1995
80C51familyarchitecture
80C51Family
Flsurc 10. PSW(ProgEm StatusWord)Reslsterin 80Csl D€vlc€s
80C51FAMILYINSTRUCTIONSET
ft'r &bit@nlrolappllcadons
setis oplimlz€d
ths 80c51inslructlon
It provldesa vadotyof iasi add€ssingmodesfor a@slifg th€
i.t6mal RAM!o ladlitat€b),teoperalionson smalldatasLuclur63
Theinstruciionsei providssonensivesupportior onebii vadablos
as a separaiadatatype,allowlngdiect bit manlpuialionin @ntrol
andlogicsystemsihai €quirs BooleanPlocessing.
ProgramstatusWord
The PrcgmmStatusword (Psw) @ntainsseve€l shtus bils lhal
rofleciihe currenlstaieof lhe cPu. The Psw shownin Figu€ 10,
€Gid€sin the sFR space.lt conlahsthe catry bil, lhs Auxiliary
Cary (i BCDoperalions),ihe two r€glslerbankl6l€cl blts,the
statusndgs
169.aPaiiybil a1dlwouser{€Fnable
Overflow
Ths Canybii, oth€rlhan seNingth€ tunciionoI a Cafrybil in
abo s€ruesas lhs "Accur.ulaioflor s
adthmeticoperaiions,
opsralions.
numbgr
oJB@lean
fte bitsRSOandRS1areusedto 6€lscloneolth€iourr€ister
banksshownin Figurc7. A numbetol inslruclionsrererlo the6€
March1995
RAMlocationsas R0throughR7.Theselectionof whlchof thefour
is b€ingreiercd to is madoon the basisof th€ RSoandRSI ai
The Padtybit €ll€cls the numberol 1sin rheAccumulalor;P = 1 li
anoddnumberolls, andP = 0 ii lh€
conlains
thoAccumulalor
of 1s
of 1s.Thusthenumber
contains
anevennumber
Accumulalor
plusP isalwayseven,Twobitsinlhe PSWaro
inlh€Accumulalor
purpose
slatusflag5.
andmaybs usedasgeneral
uncommlited
Addresalng Modes
Theaddrosshgmod6 in lh€ 80C51inslruclionsst €re asfollows:
the opeEndis sp€cffiedby an 8-bitadd€ss
In dkecladdr€ssing
fieldin rho'nstruclion.only inlena' DataFAMandsFRsc€nbe
80C51Family
80C51familyarchitecture
In indirect6ddrs6ingthe insLuclionspecifiesa .egisterwhich
@nlainslhe addressof the opeland.8o1i inlemalandextemal
M[4 canb€irdi€cilvaddr€ss€d.
Theaddrs registerlor 8-biladd€!6er caf be R0o. R1 of the
solocledbank,or lhe StackPoinlerTheaddressreqisterior l Fbli
addresse canonlybeihe 16-bitldata poiniel regisier,DPTR.
Thereqisierbanks,
@niaining
reqisters
R0ihoughR7,en !e
a@ssed byedain inslrucliomwhicherry a 'bit €gisier
soecif€iion wilhinlhe oo@deol the in6lruclion.lnslruclionsthat
acc€sslhe rcglsrersihis wayare codeeffclent,slncoihls node
€lininalsssn addr€ssb!,ie.Wh€nlho instuclionis execulsd,on€of
lhe eightreglsGFin the selecledbankis ac@ssed.Oneofiour
banks:s selecl€dat €x€cutontim€by lhs alvobanks6l6clbils in the
Reglslor€pecaticInstructions
Somelnstructonsarespeoincb a @.tain€gister Forexample,
someinsLuclions
alwayG
op€Bt6on lh€ Acclrnulator.or Dala
ropointio ir-Theopcodo
Poinlgt€tc.,so noaddEssbyteis needed
itselldo6 hai lnslruclion!lhat €t€r lo th€Accumulalora6A
assemble
asa@umulatorsogcifi
coocodss.
Th6valu€of a consianlcaniouowths opcodoln Prog€mlvemory
M O VA . # 1 0 0
loadstheAccumulalor
wlihl'r€d€dmalnumbs100.Thesam6
number
6dd bespecilied
inhexdigits
as 64H.
add|sing,
OnlypbgEmMemory€nbeaccg$edwilhindexed
andil canonJybe read.Thisaddlessingmod€is iitendodfor
rcadins
l@k-upiabl€si. Prcgram
MemoryAlGbil bas€registor
(einer DPTRor L'r6Plog€m CounleDpolnls10the baseor th€
is sei upwiih lhe lableenirynumber
lable,andli€ Ac.umuJator
Ths addressof thetableeniryin Prog€mMemoryis iomed by
dala!o lhe basepo'nter
addinqtheAccumulaior
addrcsslng
is usedln ihe'€sejump'
Anolhert}?€
ol Indexod
addEs ota iumDinstruclion
inslrucon.Inlhlscaseihedeslination
ls comDuled
as lhe sumol lhs bassoolnt€randlh€ Accurnulalof
Adthme{iclnstructions
Themenuof arilhmericinstructionsis lisrodin Tabl€1, Th6table
lndlcates
lheaddressi.g
modos!161can
b6us6dwilh€ach
roaccgsslhs<bls> op€€nd,For€/€mple,lh€
lnsr,.ucrlon
Aoo
A,<byl6>insttuclioncanbs wnflonasl
ADD
a,7FH(direcladdre$ing)
ADD
A, @R0(indiEctadd€ssins)
ADD
a, R7{€gistd add€ssing)
ADD
A. *127limmediaie
constanil
Th6sxgcurlon
tm€slistodin Tabl61 as€um€
a 121',,lHz
clock
lrequency.
Allollhearilhmetic
insirucljons
execute
in 1psexepi
theINCDPTRinstruclion,
whichlakes2Us,andtheMulliply
and
Divideinslruclions,whichtake4Us.
Not€rharany by,lsIndro IntemalDatal,lgmoryspacscanb€
inc€mont€d
wilhoutgoingthrcushlh€Accumuraloi
On€oi lh€INCin6lrucliors
op€ral66
onlhe 16-bilDalaPoinlerThe
DataPoi'n€risus6d1ogen€€le 1Fbil add€66€stor exlemal
memory,60
beingablelo increment
ii inone16-biioperation
isa
TheMULAB instruction
multiolies
iheAc@mulaior
bvthedatain
iheB egisierandpuisihe 16-bilproducl
inioihemn€ienatedB
andAccumulator
regisie.s.
ThsDIV ABinslruclion
divldssthsAccumulalorbvth€
datainlh€B
.egisier
andleaveslhe8"b'tquolient
in iheAccumulalor,
andlhe
intheB reglst€r
8-bltremaind€r
Oddlyenough,
DIV ABfindslessusein adhmetic'divide"
outnes
thanin €dix @nveBionsandprog6Bmableshiftope€tions.An
example
ol iheuseo'DIV ABin a 6d @nve'6ior
willbegiven
lalei ln 6hifloperations,
dividi.g a numb€rby 2n shift5its n bilsto
th€dghi.U€ingDIV ABto p€fom lhodivision
compl€t€s
lheshinii
thebilslhatweeshifred
out.
4LsandleaveslheB iegislerholding
The DAA insiruclionis for BCDadthmeticoperatons.In BCD
aitrmetlc,ADOandADDCinslruclions
shouldalwaysbeiollow€d
by a DAA ope€tion,to ensurethai the resuliis alsoin BCD.Note
thatDAA willnot6nven a binarynumber
[o BCD.TheDAA
ope€lionproduc€s
a .r€anhgtul
r€sultonlyaslhosecond
sl6ph
lh€ addilionof two BCDbyles,
80C51ArithmeiicInstruction3
Table1.
MNEMONIC
OPERATION
ADDRES6INGMODES
DIR
IND
REG
IMM
EXECUTION
tlME{ps)
X
SUBBA,<byl€>
x
x
INCA
x
2
INC DPTR
DECA
x
MULAB
DIVAB
March1995
x
80C51familyarchitecture
80C51Family
LodicalInstructions
Tabi€2 shM lhs ltslol 80C51losi@linslruclionsThelrstruclrons
thal oorfom Booleanop€lalions(AND,OR, ExclusiveOR NOT)on
bvds oedom the operalionon a bil_by-biiba6is.Thatis if th€
010100118,
andbt4econtains
oo110101B
A;cud;la[or@ntains
A,<byls>
ANL
000100018
holdlng
theAccumulato.
wlllleav€
modeslhat canbe us€d!o accesslhe <bvl€>
Theeddressing
ope€ndae lisi€dlnTabl62
mavtakeanvoI lhs iorms:
TheANL A,<byt6>instruction
ANL A,7FH(di€c1addtossing)
ANL A,@R1(lnd!€cladd€sring)
ANL A,R6(€glsleraddrcssins)
ANL A,#53H(irimedialsconstanl)
execule
areAccumulator-specilic
All of lhe logi€l instuciion! thst
'rhe olhelstake q$
clock).
in 1us(usinga 121\,lHz
Notelhat Booleanope€tions€n bEporiom6don €nvbytein the
intemalDalaMemoryspa€ wilholt golngthrcughlhe Accumulalor
Th6XRL<btt€>,#da!ainstruclion,for exanple,offersa quick6nd
easywayto invedponbits,a6inxRL Pl' #oFFH.
li theoDeEi'onis InEsponseto an interrupt,nol usingthe
savosthetim€andeflbdio pushil onioths siackin lhe
Accumulator
TheRotaieinstuciions(RL,A, RLc A elc ) shifl theAc'umubtor I
o tro th€leitor dgll For€bn o|,[on fie MSBrollsirLoll'e LSB
theLSB'olsirlo lheMSBpos'for'
position.
Fo'a dghrrotation,
lh€ highandlow nibblos
Th€ SWAPA Inslruclioninterch€nges
whhinthoAdlmulator This is a usotulop€€iion in BCD
cortairsa brnary
Fo_€xarpleitlheAccumLlator
manjoulauons.
num;6.whicn
ls nown lo b€ l6ssll'ar 100 it€n beouic[v
convedadto BCDby drcfollowingcode:
rvlovE B,#10
DIV AB
ADD A,B
Divldlngth€ nl]mberby 10 leavesthe tensdigitInthe lowntbbleol
th€Admulalor, andlh€ onesdigit in lhe B registerTh6swAP and
ADDinsiructionsmoveihe lsns digiito li€ highnibbioot th€
andtheonosdigitio thelownibbls.
Accumulator,
DataTransfers
Tabl63 showsthe menuof Instruclionsthal aB availablefor moving
andtheaddresslng
memory
spaces,
dataaroundwilhlntneintemal
clock'alloi
sod€slhaten beusedwilheachon€.wiih a 12MHz
oxecutein either1 or 46
iheseinsiruotions
The [4OV<desF,<src>insLuclionall@s dataio betransiersd
will'outgoilg
orSFRlocallons
be&eeFaryhro rtemarRAM
theUppsr128bvl6sofdata
Romemb€r,
theAccumulator
ihrouoh
onlvbvlndiEciaddfesing'andsFRspa@
RAM-can
beaccessod
onlybydir€ciaddr€6slng.
RAM' and
the6tackrsidss Inon-chip
Not€lhatin 80C51devic€s,
lheSlack
nd incemenis
ThePUSHinstruclion
ows urwards,
Fo'nt$ isP), lhsn @piesthe bvt€inlo lhe slack PuSHend PoP
useonv dnectaddressingto ideilt the bv16being6avedor
bvirdke.iadd6s'ing
,"rto,ed,Uuttt""sr""t it"et't"
"ccessed
means
lh€stackca4go:.to lie upper
usirorh€sPregisterTFis
128byresofRAM i',lheyaremoleme.lgdbLtrol .tosFRspace
in lhe80c51ror
of RAv a€ 1orimpl€renled
Th6Uooer128b'4es
'i ir6ioMles6orEPROVcou.teTensWrn heseoevi@silrhg
bvlesa€ losl andPoPed
sP pointsrolhe upper128,PUSH€d
bytesar€Indeleminale
TheOataTansiar Inslrucibnsincludea 16_bltMoV lhat canba
used!o inltlali@lhe oata Pointd (DPTR)lor look-uplablesin
PogramlM€moryor ior 16-bil€xlornalDalaMenoryaccases
80C5'l Logical lns:ructlons
Table2
IVNEMONIC
MODES
ADDRESSING
OPEIIAT]ON
DIR
IND
REG
IMM
EXECUTION
TIME(rs)
x
<byt€> = <byie> ,AND.A
.byt€> = <byt€>.ANDirdala
x
x
x
<byle> = <byt€> .oR.l4ata
<by4e>- <byie> xo!1
<hue> = <b!te> .XOR.#data
RIC A
MaEh 1995
RoiateACCLefr1 bit
RolateLefl lhroughCarry
RoiateACCRisht1 bit
Rotat€Rightlhrugh Carry
x
x
2
1
1
2
1
1
2
1
1
1
1
1
1
1
80C51familyarchitecture
80C51Family
Table3.
DataTransferhstructionsthat AccesslnternalDaiaMemorySpace
MNEMONIC
OPERATION
ADDRESSINGMODES
DIR
IND
REG
IMIM
EXECUTION
TIME{!s)
x
X
DPTR= l Gbitlmmgdlat€
cofstani
INC SP:MO\r@SP',<s.c>
MOV <d6st>.'@SP':OEC
SP
ACC €nd <by1€>6rch6nsedaia
XCHD A.@Ri
X
X
2
2
2
2
x
ACC and @Ri€xchanoelow ribbls
TheXCH A, <byle>insLuclioncauss5th€ Accumulalorand
addBed btie to exchange dala, The XCHD A, @Ri instruclion is
similar,bui onlylhe low nibblesa€ involvedin lhe exchange.
To see how XCH and XCHD c€n b€ u€€d io facilital€ data
manipulalions,
@nsiderlirstthe probl€molEhiltingan 8{igit BCD
numberhrodigils[oihenghl Figue 1l shom howthis can be
done us'ng dieci MOVS,and for @npad$n how il 6n be done
To ald 'n undeFlandinghowihe code
lslng XCH Instruciions.
wort€, th€ @nl€nls ol urs r€gisl€Is thal ars holdirg ih€ BCD
numbersndlh€ coni€ntof lh6 Accumulaloraro shownalongsid€
ea6h inslruciion lo indica[e lheir stalug aier the instuclion has been
Alier ihe butine has been executed, the Acdmulaior contalns the
two digiisthatweE shiiledoul on ihe dghl.Doingtherculinewilh
dir€cl MOVSuss 14 code bytes and 9l1sof exe@tlon ii6e
(assuninga 121',lHz
clock).The sameoperatlonwilh XCHSls€s
only I bytes and execuls almost lwi@ as tast.
To ishl-shinby sn oddnurnb€roidlglls,a on€-dlgltshitnust b6
Fioure12 showsa sampleol codethatwill dghl-shifta BCD number
Again,the @ntenlsol ihe
onedlgii,usin! ihe XCHDinsiruction.
Eglslersholdinglhe numberandol the Accumllatorae shown
alo.gsidoeachInsttucllon.
Firsl, point€rs R1 and R0 ae sel up io poini io lhe two bttes
-rh6.
@nlaining lh€ lsst tour BCD digns.
a loop ls execolod wblch
leavesihe lasi byte,lo€tion 2EH,holdirgthe lastt/o diqilsoi lho
shiitednumberThe poinieEare decremenled,
and the loopis
repealei ior locallon 2DH. Tho CJNE inslruction (Compare and
Jump if Not Equal) is a loop contlol thal wlll be described laier The
loop€x6cut6dlom LOOPio CJNEfor Rl= 2EH,2DH,2CH,and
2BH.Ai lhal poinilhe digillhat was originallyshiitedoul on ihe nghi
has pDpagatedto lo€tlon 2AH.Sln@that lo€tlon shouldbo l€t
wllh 0s, the lost dlgit ls moved to th€ Accumulator.
Table4 shows a lisr of th€ Data Tmnsfff lnstructons that acc€ss
€n6malDala Memory.Only indi€ci add€sEing€. be used.The
choic8 is wheiher io use a one-byte addess, @Ri, where Ri can be
eiihe. R0 or R1 of the seleoted register bank, or a twobyle addes,
to u6ing16-biladd€ssesifonly a lew k
@DPTR.Th€ disadvantag€
by,leBof €nenal RAM a€ involved is ihat 16-bil add€ssE use all 8
biisol Pod 2 as addressbus-On lne otherhand,8-biladd€sses
allow one to address a Gw bytes oi RAM, as shown in Figlre 5,
wilhod naving to sacnfie all oi Port 2. All of ihese insiruclions
execulo In 2 ps, w'th a 12[,lHz clock.
Noteihalin allenemalDaia RAIMa€esses, ihe A@umulaioris
always eber lhe deslination or solrce of ihe &la.
Th€ r€ad and wdto slrob€s to €xlgrnalRAM ar€ aclivat€d only
duringth€ €x€arlionof a MOVXi.st,uclion.Nomally th€sosignals
afe inacttus,€nd In fact ll they re nor golng to be used ar all, rhek
Dinsa€ .vailabl€as 6nfa tOlin€s.
AU.|i!diEd[ov,|i.byb!'9F
Figurel'1. shinlnsa acD Numbe.TwoDigitstoth€ Right
March1995
Flglr.12.
Shlftlng a BCO Number One Digitlo the Right
80C51familyarchitecture
80C51Family
Table4,
80c51DataTransferInstructionsthat AccessExlernalDataMemorySpace
ADDRESS
WIDTH
8 bits
16biis
16blts
Tablo
Read€rl€marMl'/ @Rl
Wdte€xt€rnalRAlt @ Rl
ReadexremalFiAM@ OPTR
wnte extemalRAM@ DPTR
t\4ovxA,@Ri
MOVX@Ri,A
MOVXA,@DPTR
MO\,,(@DPTR,A
80C51LookupTableReadInstructlons
MNEMONIC
MOVCA,@A+DPTR
MOVCA,@A+PC
OPERATION
Readplog€m memoryal (A + DPTR)
Read DbqEft m€morv at (A + PC)
Tao. 5 showsfi€ nto irst uc-onsthala€ svail.blefo'r€adlng
ac.ess
Sin@the6€Instuctions
in Prcg€mMemory'
lookuptables
onlyPEgramMemory,h€ lookuplablsscanonlvb€ rsad,nol
lf lhs tableacc€ssis io exlsrnalPrcgrsmMemorv,lhonthe read
sfobe ls PSEN.
rBt MOVC
is MOVCio!'mov6constant'The
Themremonlc
a tableof upto 256enld€s
inslruclionin Table5 en accommodats
o through255.Th€numberof ths desied enlryis loaded
numb€red
lntoihe Accumulaioiandihe DalaPointerB s€l up to poinlio |ne
oflh6labie.Then:
beginnl.g
MOVC A,@A+DPTR
oopi€slhe de5ir€dlableenlryintothe Accunulator
Th€otherMOVCinstaclionwork th€ sameway,oxceprhE
P@g€mcouiisr (Pc)is us€das ih€lablebaseandthelablais
access€dthough a subbuiino FiBt lhe numberollh€ desired
andlh€ subroutinei' €lted:
is loadodintoth€ Accumulator,
enl,ay
MOV A,ENTRYNUMBER
CALL TABLE
SABLEwouldlooklikslhis:
Thesubrouline
TABLE| MOVC A,@-A+PC
RET
iollowsthe RET(Eium) Instrudionin
Theiabl€ltseffimmediately
PrcaratrMetrory.Tl'is lype ol lab e €n haveup lo 255entd€s
255.NJrbero c€nnolbe usedbe€useat lho
nutrbecd1 lhrouq1
tim€the MOVCinslructlonis ex€clted,ths PC containslhe addross
ol nr€ RETinstruclionAn entrynlmbered0 wouldbeth€ RET
Boolean Instructlong
80C51devicescaniaina comPleteBoolean(single'bit)prcc€ssor
bits andiheSFR
128addressable
RAMcontains
Theintemal
bilsaswell.Allol thepon
upto 128add€ssable
spac6caf suppon
andeachone@n bs lreated5s a
llnesare bit-addr€ssable,
sepa€iesingl€-bilporl Theinstructlonslhat accessthosebiis aro
bEnch6s,buta complelsmenuol move set
ni iustconditional
Thesekindsorbit
oR, andANDinstruclions
de;r.complem€m,
silh ahy
'rthnedur€s
othor
i/l
obla)ntd
opfttrons a@noteady
amountof btte oneni€d$ltware
Theinsiructionsetlor the Booleanproes6or is shownin Tablo6 All
bil acc€ssesaroby di€ct addrsssing
7FHa€ ln theLower128'andbil
BitaddBs€sOoHlhrough
a€ in SFRspace
FFH
thrclgh
808
address*
1995
lvlarch
EXECUTION
T|MEfus)
2
2
2
2
OP!RATION
]IINEMONIC
TIME(lll)
EXECUTION
2
2
€n bemovedto a portpin'
Noteh@ oasilyan intemalllag
MOV C,FLAG
MOV P1.0,C
bitinthe
FLAGlsthenarn€of anvaddr€ssable
Inthis6xample,
An l/Olins(theLsBol Port1, inlhis
Lower128or sFR6pac€.
onwhetherlho flagbit i5 1 or 0
es€) is set or cl€arcddePending
TheCarrybhInthePSWls usedaslh€single_biiAccumul.loror
ihe Booloanpro@ssoiBit hsirucliorc that referio th6 Carrybit as
C assembleas Carry'specificInstuc{on€(CLRC etc ) TheCarv
bit alsohasa directaddress,.inc€ lt residesin lhe PSWr€gisier'
whichis bit-addrossable.
Noi6lhat ihe Bool€anInsiruciionset includesANLandORL
oR) op€€lionAnxRL
butiot rhexRL (Excllslve
ope€ljons,
opeEiionis slmpleto implementin softwareSupposeior €xample,
It is Bquirodio lom tho ExclusiveORof two bils:
C - bltl .XRL,bit2
Th6sofrwar€to dolhat @uldbe as bllowsl
MOV C,bltl
b|I2,OVER
JNB
C
CPL
Fi6! b[1 is rovsd lo the Carry'lf bll2 = 0 thenc nowcdniaintth€
cor€ct result.Thal ls, bitl .XRl bii2 = bill li bii2 = 0 Onlhe olhsr
of lhecor€cl
lhecomplemenl
hand,il blt2= 1, C nowcontains
r€suii.lt nsedonlybo Invened(CPLC) io completeih6 opeEtion.
Thiscodeuseslhe JNBinslruction,oneof a 66ios of bil-t6sr
bilis 66t(JC JB
a jumpiflhe addrsssed
execulg
inslruotionswhlch
JBC)orlt theaddr€s*dbills notsei(JNc,JNB) lnlheabov€
]s
6s;, b[2 is beinqtested,and!i bit2= o thecPL c Instruciion
lh6lumpifth€add€ss€dbltissel'€ndalsocloars
JBC€xecutes
-lhus f,a! en betesledandclearodln oneop€raiionAll
a
th€ iit.
add.sabl€, solhePadtybil orthe
ih€PSWbitsarsdireclly
io lhabirtesl
arsalsoavailable
geieralpuDossnags,tu €xample,
lo the
is specif€d
addrsssiorthesejumps
Th€dslination
m€norv'
in
PbsEm
ldd€ss
ah
6ctu.l
labal
ot
bv
a
a$wbJet
W
H.w6v6rlh; d€stlnationadd€ss assenblesio a €lalive ofisei
whicl s added
by1€
otsse!
TFi6ls a sig.ed(twos compl€menr,
by1e.
:' thsjumpis 6xecJted
srilhmslic
6 h€ Pc in Moa complem€nl
Themngeof thejwp is the.€iore-128 to +127ProsEmr"4emorv
blt6s relauvgto lh6 filsi bvt€iollowinglhe inslruclion
80C51familyarchitecture
80C5'1Family
80C5'lBooleanlnstructlons
t a D t eo .
MNEMONIC
ANL
C,bii
oRL
C,bti
oRL
C,/bil
MOV
C,bit
l',lOV
blr,c
EXECUTION
TlilE (ps)
OPERANON
C=C.AND.bit
C = C.AND..NOT.bil
2
2
2
2
1
2
c:c.OR..NOlbll
blt=C
'I
c
'I
CLR
SETB
SETB
CPL
C
b|t
1
1
1
bit-1
C= -NOT.C
blt=.NOT.bll
c
'I
2
2
2
JC
JB
JNB
bit,r€l
2
2
JBC
Table7.
Unconditional
JumDsin 80C5'lDevlces
MiIEMONIC
EXECUTION
TIME(ps)
OPERATION
2
JMP
@A+DPTR
RET
REfI
NOP
JumDInstructions
Tabl€7 showsihelislofuncondiilonaljuhpswith
exetutlon
tlmeicr
Thei.bl€ lislsa singl€"JtlP add/ Insruc on,bul Iniacl lh€rsar€
whlchdlfferIntheiornatof ths
lhEeSJMP,
LJMa€ndAJMP,
JIMP
is a geredcmnemonicwhlch
€n be used
d€stinarlon
address.
tfthepEgfammerdo$
nolere whichwaylh6jumpis encoded.
TheSJMPinstruclionen@deslhe dEstinalion
addr€s5aBd reralive
above.TheJnstaoonis 2 bt14long,
ofsel,asdescdbed
@dsrirg o'll.€opcode
dndh€ cla'iv€o"s€lbla€,Tf6jurp
dislanc€ls limlt€d10€ rangsof-128 1o+127b}ls elalive to lhe
followingihe SJMP
lnslruction
enodesthedesiinalion
addes asa 16'bit
TheLJMPInslruc{on
consiant.Thelnstructionis 3 byteslong,consislingof the opcode
andflvoaddressbyt$. Thedeslinalionadd€6scanbe anywhe€in
lh€ 64k PbgramMemoryspace.
The,IJMPinsltuclion
en@des
thede6tination
addr€$aBan 11-bil
@nstant,Th6lnslruclionis 2 by[eslon!, consistingof ihe opcode,
biis,iollowed
bvanother
whichil3elfconleins
3 0i rho11address
by.reconlainins$e l@ 8 bils of th€ d€sunafonadd€38.Whsnlh€
inslrucionls oxocuted,ihe* 11bils aresimplysubslituiedfor lhe
ow11biisinihePC.Thehigh5 bitsslaylhs s€fi6.Hsncoth€
dgslinationhasto bewithinlhe same2k blocks the instruction
March1995
In all casesihe p.ogEmmerspecinesihe deslinaiionaddres to lho
assembler
inthesameway:as a labelor asa ! 6-biiconsianl.
The
a6.€mbl€r
willpulth€deslinalion
add€6sintolhecorectfonnallor
lhegiveninslruction.
lf ihefomatrequicdbytheinstruciion
willnoi
lo lh€sp€cifigd
suppod
lhs dislance
d€slnaionadd€ss,a
'Doslnalionout oi rang6'mossagois witten Intoths Listtlo.
Insttuctlon
Th6
Th6Jl',lP@A+DPTR
suppods
casejumps.
destnation
addrs is compuied
atex,.cution
timeasihesumoi ihe
DPTRis selup
16-bitDPTRrogisl€r
andth€A@umulalo.
Typically,
wiihtneadd€ssofajumptable.Ina s-waybranch,
ior eEmple,an
'lhs
inleger0 though 4 i5 load€dintoth€ Accumulator cod€lo be
executedmightbe as iollows:
MOV DPTR,#JUMPTABLE
MOV A,INDEX-NUMBER
JMP
@A+OPTR
The RLA instrucuoncoivsris th€ ind6xnumb€.(0 thlough4) to an
iherange0lhrough8, because
eachenlryinthe
evonnumberon
lumplableis2 bles lonoi
JUMPTABLE:
riJMP CASEO
r'iJMP CASE1
PiJMP CASE2
AJ]VP CASE3
AJ]\,IP CASE4
-:l
80C51familyarchitecture
80C51Family
builhe€ ar€twoof
addl inslrucllon,
Table7 showsa single'oALL
th€m,LCAILandACALL,whichdifierin th€ iormath whichh5
add€ssi5givenio iheCPU CALLis a gonsric
subouline
notoae
en b€lsed ifth€pogEmmerdoos
mnemonlcwhich
whichwaythe addressis en@ded,
The LCALLinstruclionus€sthe 16_bitaddre$ iomat, and$e
subrouiine€n boanylvhe€inthe €4k ProgramMomoryspacs.
fomal,andthesubroutin€
uss th€ 11-bh
TheACALLi.slrucllon
lhe
lollowing
muslbeinihesne 2k blockasih€ insiruclion
ACALLspscifiesihe subouljnoaddEssto th6
n anycase,ih€ programmer
constaniTh€
inthesamoway:as a labslor as a 16_bn
assenblsr
wlll putthe addr€ssinlolh€ corfsctiomat for ho glven
assembl€r
Suboltin€! shouldendwith a RETinslruclion,whichrelums
eieollion to th€ nslructiontollowing th€ CALL
RFII ls used!o rotumf.oman InterruptBervic€routineTh€only
differencebetveenRETandRETIls ihat RETItslls lhe intenpl
61110'sysl€nliat iheinl€tuptinproqe*isdor€ ltLhereisro
rleruplin prcg€ssallh6tmeRET|lsoxecutedln€nlie RET|is
tunclionallyid€ntjcallo REL
Table8 showsihe lisl oi onditionallumpsava 6bl6lo the 80c51
addr$sbvlhe
ihedesljnatlon
speclry
userAlloflh€sejumps
r€lariveoibsl melhod,andso are limit€d!o a j!6p dislancsoi -128
jump
tollMinstheconditonal
io +127b!4estrcn lhs insiruction
io
the
6pecii€s
hNev€r,
the
user
lmpodantlo nol€,
Instruclion,
th€ectualdesunalionaddr*3 lh€ samewav as lhe other
assembler
ju.iips:asa labelor a 16-bilconstani
Thereis no2611'blt in ths PSW.TheJZ andJNZinst uclio.s test
daiafotthatcondilion
theAc.umulalor
The DJNZInsiruclion(D€cremeniandJlmP il NotZero)is lor loop
conlrol.Toexecutea loopN limes,loada counierbvtswfthN and
t€rminatelh€ loopwilh a DJNZto lhs boginninsof lh6 looP,as
shdn belowforN = 10.
MOV
COUNTER,#1o
DJNZ
COUNTER,LOOP
(conpa€ andJumplI NotEqual)canalsobe
ThoCJNEinsttuctlon
usedfor loop@ntol ss in FiguE 12 Twobles arespeciiiedin lne
opeEndi€ld of ihe inslruclion.Thejumpi6€rcclted onlvif ths i{o
bttes dronot€qual.In lhs €r€6ple of Fjgure12,lhe nvobyteswe€
in Rl was2EH.
Th€iniUaldaia
daiai. R1andihecon6lsnl2AH.
andihe
Everylims ihe loopwa! €x€cuGd,R1wasd€cremenlBd,
loopingwasto continueunil the R1datareached2AH
ihan"
is in'greaierihan,less
ofthisInstrucijon
Anolher
spplicaiion
Thetwo byt€sin the operandneldae tak€nas
comparisons,
ihenlhoCarry
It thefirstis l€ssthanlhesecond,
lnsignedinteg€rs.
bit is sei (1). ll ths fiIst ls lGaier thanor equalio tho se@ndihen
CPU Tlmlng
er be
haveaf on{hlposcillalorwhich
microconLollors
All8OC51
usedil d€sled 6 ii€ clocksourc€for the cPU Tous€lhe on chip
oscillator.conreota crvstalor ceErnicr€sonalorbel't€enthe
xrALl andXTAL2pinsoi lhe micocontoller,andcapacitoBio
soundas shownin Fig'rrc13.
Examplesol howto ddveihe clockwlih an ext€rnaloscillalorate
(8051elc)th€
Noteihatinlh€ NMosdevic€s
shownh Fisure14.
qeneratoi
divestheinienalclock
XIAL2pinactLrally
signalalthe
In ihe CMOSdevi@s(80C51.e[c.),ihe signalat lhe XTALIpin
ddvesthe intemalclockgeneraior'The intemalclockgenerator
definoslhe s€qusnceof slateslhat makeup lhs 80c51machino
Figur.l3, Usingtho on-Chiposclllator
CondltionalJumpsin 80C51Devlces
Table8.
i,INEMONIC
OPETIATION
DIR
IVODES
AOORESSING
tMtllt
tNo
2
JZ PI
2
JNZ el
2
DecremsnlandjufiP lf notarc
X
x
l4arch1995
EXECUTION
TIME(Fs)
10
X
2
.Fhil'p! Semi@nduciors
80C51Family
a. NMOSor GMOS
80C51familyarchitecture
b.N OSOnly
Figuc14.
Uslng d E.b.mal Clock
MachlneCycles
A machi.e cycl€ @nsists oi a sequene of 6 stal6, nunbercd Sl
lhrough S6. Esdr sial6 tng l*15 lor lwo cdllaror o€riod& Thus a
machins cycl€ ldk€6 12 Gcillaior pedo& o. 1ps it th6 @ittator
Each siale is divided inlo a Phas6 t haf and 6 Pba* 2 han
F gure 15 shors that f€tch/sx€dne sequenB in sraias .nd phas
for vanous klnds of inslrudjons. Nofinally two progEm blch€s ard
generaled dudng 6ach nachine clcle, eEn if ihe instruction b€ing
€x€culsd doosn l €qui€ il. f ihe inslruclion b€ing oxedied do6n t
n€ed mor6 code btls, :he cPU simply lgnor€s ihe qt-a let h, and
lh€ Prog6m C-unteris nol in@me.ted.
Exe@tion ofa one{ycle 'nstruclion (Flgu€s 15a and l5b) begins
dunng State 1 ol lhe machine cycle, wh€n ths opcode is tatded into
the Inslruciion R€gisier,A s€cond fetc*' o@uB dunng 54 of ths
sans machins cycl6. Erecu$on is @mDlele at ihe ed of Sial6 6 of
Th6 MO\X inslruclions lake lwo machine ctcles io ei€olba. No
prcgEm letch is geneEted dudng ihe s€cond ctd6 of a MOVX
insiruclion. This is tho only lims prcg€fi t€lchs ae sklpped. Ihs
ietch/oxeculs $qu6nl6 ior MOVX in€lruclioN is shM in Flgur€
1&.
March1995
c. CII|OSOnly
Tt'€ fatch/exe@te
sequme ar€ th€ sane whetherthe PbgEm
Momry b intehal or extemal10ths chip.Executrion
iimesdo nol
d€p€ndonwfietherlhe PrcgEmM€noryis intemalor extemal.
Figue 16shtr lhe slgnalsandliminginvoted in progamf€tches
whd ihe PogramM€moryis extemal.lf ProgramM€noryis
e{emal, th€nlhe P.ogEmMemoryrcadsbob€FSENis nomatty
aclivat€dlui@ permacbineqcle, €s shoM in Figure16a.tf an
aclE$to exlemalDala grnoryo@uB,as shownin Flgur€16b,
leioEE_FSareskipped,b@us the addressanddalabusare
b€lngus€d60rthe DalaMemoryacc€ss.
Notethata DalaMemry bus cydelaks twie as muchtimeas a
PogEn Memorybuscryde.Flgurc166howstne relaiiveiimingof
rh€addrss beingemitiedat Ports0 and2, a.d of ALEand
PSEtr AIE is us€dio latchthe lowadd€ss byt€liom Pointolhe
Whentr'e CPUis sxeculi.gfromintenal Pbg,am l\4€mory,
PSENis
notach€ied, and pmgramaddr€ss€sa€ nol emitled.Howeve.,
ALE6r inuesio b€ actival€dlyice per machinecycleandso it is
availablo63 a d@t oulputsiqnal.Nols,how6v€r,thatoneALEis
sldpp€ddud.s the ddlion orihe MOVXjnsLuclion.
80C51Family
80C51familvarchitecture
*-_t___
a. l.byte, l.yclo
l.struclion, e,9., INC A
b. 2-byt€,1+ycle Inslructlon,..9., aDD a,#data
I
I
I
@de
{db€rd)
c. l.byte,2-cycl€
In.lructlon,e.9.,INCDPTR
tbb
opoe (dserd)|
I l.--,-
d. MOVX(1-b'te, 2.cycle)
In 80C51FamilyD.vlces
FiguB15. StateSequ€nce
12
'
-Phil,psScmlconductoB
80C51Family
80C51familyarchitecture
I" |;] J ":i":"i":'
[" p"i'""ii.
" F"l
I
PcLdr
FI
"+,rT"r'-F
Flgure16, Bu€CycleEin 80G51FamllyDovlc€sExecuting
fromExtemalProgramM€mory
80C51Family
80C51familyarchitecture
(MSB)
(MSB)
(LSB)
X
ES
ET1 EXI
(LSB)
EXO
Olsabl€s
allint€rupts.
llFA= o, io
inrenupr
wlllbeacknowl€dg€d,
lf EA - 1,
eachintoruplsourco
is individually
enablod
ordls€blod
bys€ttingorcl€adns
lP,4
ES
tE.6
tE.5
tE.4
ET1
rE.3
Enabl€sor dlsabl* lh€ limer 1 Overflow
int6n'rpt.lr ETl = 0, the nmq 1 inlerupi
tE.2
Enabl$or disabl$ExtonalIn!6rrupi
1lf EXl = 0, Engmd Int€nuptI i€dsbl6d.
Enablesor disabl* ihe Timer0 Overfow
InEEupr.
trcru = u,he Imeru hcrupr
ETO
tE.1
EXO
tE.0
lP3
E.ablesordisables
ihoSsri€lPorl
Interupt.lf ES = 0, ihe SedalPorl
lP.2
PTO
lP.1
lPo
Enabl* or disbles ExetemalIntenupl0.
ll EXo= 0, Exiemalln[erupi0 is diebled.
Flgu€ 16. In6.ruptPnodty(lP)Rogbr€r
Flgur€17. Int.rupt Enable{lE)R.glster
"-('
"4,
()'<'r
"4,
.4,
I
Flgur€ t9, Inl.mpt Contrc!Ay3tem
l'/arch1995
pnoriv
Denn6lheSedalPoriinteFupl
l6v6l.PS= I prcS€msillo ihehisher
pdodtylevel.
,]'imer
Defin6 lhe
1 inierupt priorit
level.PTI = 1 programs
ll b $€ higher
pnodtylevel.
Oefn€ the Ext6malInt€nuptI prloriv
iitothehigher
level.PX1= 1 programs
pnodlytevel.
Enabl€s
or disables
lhe llmer0 Inlerupt
piorily l6vel.PT)= 1 prog€ns it rc th6
highe!priorivlevel.
Dolin€sth€ Exl6melht€rrupl0 prlodly
le@|.PXo= 1 proShms
lt to lhehlgher
pdoriiylov6l.
Piilips SemiconductoE
80C51familyarchitecture
80C51Family
noted(Figue3),lheseruice
rculineioreach
inieruptb€gins
ai a
IntefiuptStructure
The80C51anditsROMlessand
EPROM
versions
have5 inierrupt
$ur@s:2exteinal
intsrupts,
2 timerini€Rpis,andtheserialporl
pushed
is automalically
Onlylh€Program
Count€r
ontoiheshck,
notlhs PSWor anyolherregislerHavingonlylhe PCaulomalically
savsdallowslhs prcgBmm€rio
decid€howmuchlimeshouldbe
sp€ntsavingolher€gislars,This enhan@sthe idempt response
lime,albeitatthe
expense
ol 'ncEasing
ille progEmmels
burden
ot
f€sponsiblllty.
As a r€sult,manyInlampl tunclionslhat ai€ typic€lin
conttolapplications
toggling
a podpinlorexample,
orrcloadins
a
timeior unloading
a sedalbuffercanonenbecompleied
inle$
limelhanit iakesotherarchiteotuEsto compleie.
Whariollows:s anovetuiewof ihe interruprstructlreior th€ d€vlce.
l\,{o€d€ralledInfomatlonior spocifrcmonb3r6of lh€ 80C51
deivalivefam y is providedin lalsr chapla6of lhis uer's suide.
Eachinierupi solrce canbe individually
enabledor disabledby
s6ilinsor cleainga bilinth6SFRnam€dlE (lnt€ruptEnable).
Thi6
Fsisl$ alsocodainsa globaldisb16bit,lvhichcsn b6 cleared!o
disableall inlenpls at once.FiguB 17 showsihe lE rcgister
Slmulatinga Thl.d Priorlty LevolIn Software
Som6appllcauons
€qulfs morelh€nhlo prlodlylsvelsthal are
prcvid€d
byon-chip
hadwafein 80C51d€vic66.ln
lh6s€cas€s,
r€lslivglysimpl66onws€canb€ s.rit€. lo poducgth€ sam6€fecl
as a lhird pioily lev€|.Fi€t, inlsmpls t'at €€ to hqv€high€r
pnodtylhan1 a€ assigngdto pnodty1 in lh6 Inloftlpl Pdoity (lP)
rcgisterTheseNicercutineslor pnodty1 inieruptslhat are
slpposedto be lnterrupteble
by pdonly2 interruplsarewriltento
lhefollowhgcodol
Include
poqEmhedio on6oi
Eachinteruplsolre €n alsobeindividlally
lwoprio ly levelsbyse$n! orcleadng
a biiintheSFRnamedlP
Flgurc18showslhe lP egislerA loepriorily
{lntgruplPrlodly).
'nlerupt canbe lnlerupt€dby a hlgh-pnonlyht€rupt, but nol by
anotherlow pdontyinierupt.A high-piorilyinteruptc€nt b€
inGFupied
byanyolherin!6mptsour@.
ll &o In16ruptrequestsof diferenlpriontybvels are recelved
lf Intsrupl
reqlestofhigherpdonvisseNlced.
sjmullan€ously,lho
an
requeslsoilhe sam€prloily levelarerecelvedslmullaneously,
inlemalpollingsgqu€nc€detefmlneswhlchrgqueslls s€rulcod.
Thuswithineachpdontybvel the€ i3 a secondpdodt 6lruclure
sequen@.
Figure19sho$ howihelE
dgt€rrnhed
bylhepolling
workio dstermin€
whichlt
andlP€glsle|sandihepolling
sequence
anvinleruDtwillbe 66Rlced.
PUSHIE
I''OV IE,#MASK
CAIL LABEL
(executeseruie outine)
IE
RET
LABEL:
InopeElion,
alllheintemplflagsarelatched
intolheinteFupl
cont'olsystemduringSiale5 of everymachinecycle.Theemples
thefollowing
machine
cycle.lilhe nagbran
ar€polledduring
enabled
intemplisfoundto b€s€l(1),thoInlgnl]pl
sysi€m
genefatesan LCALIlo lhs apprcpnat€loc€lionin Prcg€m Monory
blockEthe
inleFupt.
Severa
I condilione
unlosssomeoiier@ndilion
@nblockan inl€rrupl,anong th€mthat an Interruptot equalor
hisherp orjlylev€lis alr€adyin progrsss.
As soonas a.y pnofty interupl ls acknowledged,
the lnierupt
(lE)r€glster
is edefrned
2
so astodisableallbutprjoniy
Enablo
inteftupts.lh€n a CALLto LABE! ex€cut€slh€ RETIinst.uclion,
whichclearsth€ piodly 1 int€fiupi-in-prog€ssfip-flop.At lhis poinl
anypdonv 1 inteiruptthal b efsbled can be ssrviced,bul only
priority2 Inlenpls ars 6nsbl6d.
POPing
lE restorstheodginal
enablebyte.Thena nomdREI
{ralherlhananotherRETI)is usedto terminateihe seMceoutine.
Theaddlilonal
$frwareadds1ojrs(ai 12MHz)topdoity
1
q€neraled
LCALLcauses
iheconienls
ofthe
Thohardwar+
PrcgramCoun!€rio b6 pushodinio ihe stack,and eloads ihe PC
wilhth€ beginningaddr€ssof th6 serulcebuune.as pfevlously
March1995
15